Verilog FSM输出从未设置
我在使用gtkwave在iverilog上模拟以下FSM时遇到问题。当在gtkwave上查看时,测试台的输入会发生变化。另外,我不认为逻辑是错误的。也没有编译错误,但仍然没有输出。我不能纠正这个错误 代码:Verilog FSM输出从未设置,verilog,Verilog,我在使用gtkwave在iverilog上模拟以下FSM时遇到问题。当在gtkwave上查看时,测试台的输入会发生变化。另外,我不认为逻辑是错误的。也没有编译错误,但仍然没有输出。我不能纠正这个错误 代码: module seq_0110(sequence_in,clock,reset,detector_out ); input clock; // clock signal input reset; // reset input input sequence_in; // binar
module seq_0110(sequence_in,clock,reset,detector_out
);
input clock; // clock signal
input reset; // reset input
input sequence_in; // binary input
output reg detector_out; // output of the sequence detector
//parameter Zero=3'b000, // "Zero" State
// One=3'b001, // "One" State
// OneZero=3'b011, // "OneZero" State
// OneZeroOne=3'b010, // "OnceZeroOne" State
// OneZeroOneOne=3'b110;// "OneZeroOneOne" State
reg [1:0] current_state, next_state; // current state and next state
// sequential memory of the Moore FSM
always @(posedge clock, posedge reset)
begin
if(reset==1)
current_state <=2'b00;// when reset=1, reset the state of the FSM to "Zero" State
else
current_state <= next_state; // otherwise, next state
end
// combinational logic of the Moore FSM
// to determine next state
always @(current_state,sequence_in)
begin
case(current_state)
2'b00:begin
if(sequence_in==1)
next_state <= 2'b00;
else
next_state <= 2'b01;
end
2'b01:begin
if(sequence_in==1)
next_state <= 2'b10;
else
next_state <= 2'b01;
end
2'b10:begin
if(sequence_in==1)
next_state <= 2'b11;
else
next_state <= 2'b01;
end
2'b11:begin
if(sequence_in==1)
next_state <= 2'b00;
else
next_state <= 2'b01;
end
default:next_state <= 2'b00;
endcase
end
// combinational logic to determine the output
// of the Moore FSM, output only depends on current state
always @(current_state)
begin
case(current_state)
2'b00: detector_out <= 1'b0;
2'b01: detector_out <= 1'b0;
2'b10: detector_out <= 1'b0;
2'b11: detector_out <=(sequence_in==1)?1'b0:1'b1;
default: detector_out <= 1'b0;
endcase
end
endmodule
对于输入刺激,输出(
检测器输出
)始终为0
将检测器输出设置为1的唯一方法是在以下语句中:
2'b11: detector_out <=(sequence_in==1)?1'b0:1'b1;
我将
=1中的时间序列\u减少。这将在时间115时将探测器设置为1:
0sequence_in=0 detector_out=0
95sequence_in=1 detector_out=0
115sequence_in=0 detector_out=1
125sequence_in=0 detector_out=0
155sequence_in=1 detector_out=0
195sequence_in=0 detector_out=0
我还有几个其他的建议。对于您的2个组合<代码>始终块,您应该考虑使用隐式敏感列表(<代码>始终@ */COD>)和阻塞赋值(<代码>=)。
initial
begin
// Initialize Inputs
$dumpfile("seq_0110.vcd");
$dumpvars(0,seq_0110_t);
$monitor($time,"sequence_in=%b detector_out=%b",sequence_in,detector_out);
sequence_in = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#30;
reset = 0;
#45; // <------ more delay
sequence_in = 0;
#10;
sequence_in = 0;
#10;
sequence_in = 1;
// #20; <------ commented out
// sequence_in = 1; <------ commented out
#20;
sequence_in = 0;
#20;
0sequence_in=0 detector_out=0
95sequence_in=1 detector_out=0
115sequence_in=0 detector_out=1
125sequence_in=0 detector_out=0
155sequence_in=1 detector_out=0
195sequence_in=0 detector_out=0