verilog和gate在32不正常工作时

大门

module andgate
#(parameter Port_Num = 2, 
 parameter WIDTH=8) 
 (
 input [(WIDTH-1):0] a,
 input [(WIDTH-1):0] b,
 input [(WIDTH-1):0] c,
 input [(WIDTH-1):0] d,
 input [(WIDTH-1):0] e,
 input [(WIDTH-1):0] f,
 input [(WIDTH-1):0] g,
 input [(WIDTH-1):0] h,
 output [(WIDTH-1):0] q
 );
 assign q = (a & b & c & d & e & f & g & h);
endmodule

angate_sim酒店

`timescale 1ns / 1ps
module andgate_sim();
    // input 
    reg a=0;
    reg b=0;
    reg c=1;
    reg d=1;
    reg e=1;
    reg f=1;
    reg g=1;
    reg h=1;
    //outbut
    wire q;
    andgate #(8,1) u(.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.q(q)); 

    always #100 a=~a;
    initial begin
        #100 a=1;
        #100 begin a=0;b=1;end
        #100 a=1;
        #60000000 $finish;
    end

    initial
    begin            
        $dumpfile("wave2.vcd");        
        $dumpvars(0, andgate_sim);    
    end

endmodule

当我测试测试台时，它像这样正常工作

iverilog -o Ex2 andgate.v andgate_sim.v
vvp -n Ex2 -lxt2
gtkwave wave2.vcd

`timescale 1ns / 1ps
module andgate32_sim( );
// input 
 reg [31:0] a=32'h00000000;
 reg [31:0] b=32'h00000000;
 reg [31:0] c=32'hffffffff;
 reg [31:0] d=32'hffffffff;
 reg [31:0] e=32'hffffffff;
 reg [31:0] f=32'hffffffff;
 reg [31:0] g=32'hffffffff;
 reg [31:0] h=32'hffffffff;
 //outbut
 wire [31:0] q;

andgate #(8,32) u(.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.q(q)); 


always  #100 
    begin
    a <= 32'hffffffff;
    end
always  #200 
    begin
      a <= 32'h00000000;
      b <= 32'hffffffff;
    end
always  #300 
    begin
    a <= 32'h007fa509;
    end
always  #400 
    begin
    a <= 32'hffffffff;
    end 


initial  begin
 #100 a <= 32'hffffffff;
 #100 begin a <= 32'h00000000;b <= 32'hffffffff;end
 #100 a <= 32'h007fa509;
 #100 a <= 32'hffffffff;
 #60000000 $finish;
 end

initial
begin            
    $dumpfile("wave2-2.vcd");        
    $dumpvars(0, andgate32_sim);  
end

endmodule

然后我试着做一个像这样的AND门*32

iverilog -o Ex2 andgate.v andgate_sim.v
vvp -n Ex2 -lxt2
gtkwave wave2.vcd

`timescale 1ns / 1ps
module andgate32_sim( );
// input 
 reg [31:0] a=32'h00000000;
 reg [31:0] b=32'h00000000;
 reg [31:0] c=32'hffffffff;
 reg [31:0] d=32'hffffffff;
 reg [31:0] e=32'hffffffff;
 reg [31:0] f=32'hffffffff;
 reg [31:0] g=32'hffffffff;
 reg [31:0] h=32'hffffffff;
 //outbut
 wire [31:0] q;

andgate #(8,32) u(.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.q(q)); 


always  #100 
    begin
    a <= 32'hffffffff;
    end
always  #200 
    begin
      a <= 32'h00000000;
      b <= 32'hffffffff;
    end
always  #300 
    begin
    a <= 32'h007fa509;
    end
always  #400 
    begin
    a <= 32'hffffffff;
    end 


initial  begin
 #100 a <= 32'hffffffff;
 #100 begin a <= 32'h00000000;b <= 32'hffffffff;end
 #100 a <= 32'h007fa509;
 #100 a <= 32'hffffffff;
 #60000000 $finish;
 end

initial
begin            
    $dumpfile("wave2-2.vcd");        
    $dumpvars(0, andgate32_sim);  
end

endmodule

波浪中没有这样的东西

iverilog -o Ex2 andgate.v andgate_sim.v
vvp -n Ex2 -lxt2
gtkwave wave2.vcd

`timescale 1ns / 1ps
module andgate32_sim( );
// input 
 reg [31:0] a=32'h00000000;
 reg [31:0] b=32'h00000000;
 reg [31:0] c=32'hffffffff;
 reg [31:0] d=32'hffffffff;
 reg [31:0] e=32'hffffffff;
 reg [31:0] f=32'hffffffff;
 reg [31:0] g=32'hffffffff;
 reg [31:0] h=32'hffffffff;
 //outbut
 wire [31:0] q;

andgate #(8,32) u(.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.q(q)); 


always  #100 
    begin
    a <= 32'hffffffff;
    end
always  #200 
    begin
      a <= 32'h00000000;
      b <= 32'hffffffff;
    end
always  #300 
    begin
    a <= 32'h007fa509;
    end
always  #400 
    begin
    a <= 32'hffffffff;
    end 


initial  begin
 #100 a <= 32'hffffffff;
 #100 begin a <= 32'h00000000;b <= 32'hffffffff;end
 #100 a <= 32'h007fa509;
 #100 a <= 32'hffffffff;
 #60000000 $finish;
 end

initial
begin            
    $dumpfile("wave2-2.vcd");        
    $dumpvars(0, andgate32_sim);  
end

endmodule

实际上，它应该是wave2-2.vcd中的一些东西。

---

您能帮助我吗？

您正在尝试运行另一个已编译的测试台Ex22，而不是Ex2

提示：您可以使用参数并将其传递给实例化，如下所示：

localparam WIDTH = 32;
localparam Port_Num = 8;

// input
 reg [WIDTH-1:0] a=32'h00000000;
 reg [WIDTH-1:0] b=32'h00000000;
 reg [WIDTH-1:0] c=32'hffffffff;
 reg [WIDTH-1:0] d=32'hffffffff;
 reg [WIDTH-1:0] e=32'hffffffff;
 reg [WIDTH-1:0] f=32'hffffffff;
 reg [WIDTH-1:0] g=32'hffffffff;
 reg [WIDTH-1:0] h=32'hffffffff;
 //outbut
 wire [WIDTH-1:0] q;

andgate #(.Port_Num (Port_Num), .WIDTH (WIDTH)) u(.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g),.h(h),.q(q));

---

为我工作，带着艾维洛格。我看到waves.btw，可能与此问题无关，但最好不要在代码中的任何地方使用非阻塞赋值。@Serge@TomServo感谢您的输入，但上面的示例中没有顺序时钟逻辑。NBAs最终可能会在代码的其他部分创建种族。@Serge同意，你当然是对的。对于新手来说，你先前的建议可能会被误解成一种非常有害的方式。有人可能会将其解释为在任何代码中都不使用NBA，比如在CYou中不使用scanf。伙计们太好了，我用vivado做测试台，但我不知道vivado创建的测试台文件中有什么。