一次实现2个七段的VHDL
这是我的作业。我们的任务是设计一个VHDL组件，提供基本的秒表功能。您的设计应从零开始，并且能够在最右侧的7段显示器上最多数到20（除以下说明外，其他两个显示器应为空白）。按下中间按钮可启动和停止计数。向下按钮将计数器重置为00。如果计数达到20，板上的16个LED将创建一个复杂的胜利模式 我如何在两个不同的7段上同时显示不同数字上的两个数字一次实现2个七段的VHDL,vhdl,Vhdl,这是我的作业。我们的任务是设计一个VHDL组件，提供基本的秒表功能。您的设计应从零开始，并且能够在最右侧的7段显示器上最多数到20（除以下说明外，其他两个显示器应为空白）。按下中间按钮可启动和停止计数。向下按钮将计数器重置为00。如果计数达到20，板上的16个LED将创建一个复杂的胜利模式 我如何在两个不同的7段上同时显示不同数字上的两个数字 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.all; entity
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity lab_3 is
Port (
-------------led output-------------------------------------
led: out std_logic_vector(15 downto 0);
-------------button inputs----------------------------------
btnc: in std_logic;
btnd: in std_logic;
-----------7 seg outpus--------------------------------------------
seg: out std_logic_vector(6 downto 0); --MSB=a: LSB=g
-------------7 seg enables----------------------------------------
an: out std_logic_vector(3 downto 0)
);
end lab_3;
architecture Behavioral of lab_3 is
------decimal seven segment display--------------------------CONSTANTS
constant ZERO_7SEG: std_logic_vector(6 downto 0) := "1000000";
constant ONE_7SEG: std_logic_vector(6 downto 0) := "1111001";
constant TWO_7SEG: std_logic_vector(6 downto 0) := "0100100";
constant THREE_7SEG: std_logic_vector(6 downto 0) := "0110000";
constant FOUR_7SEG: std_logic_vector(6 downto 0) := "0011001";
constant FIVE_7SEG: std_logic_vector(6 downto 0) := "0010010";
constant SIX_7SEG: std_logic_vector(6 downto 0) := "0000010";
constant SEVEN_7SEG: std_logic_vector(6 downto 0) := "1111000";
constant EIGHT_7SEG: std_logic_vector(6 downto 0) := "0000000";
constant NINE_7SEG: std_logic_vector(6 downto 0) := "0010000";
constant TEN_7SEG: std_logic_vector(6 downto 0) := "1000000";
constant ELEVEN_7SEG: std_logic_vector(6 downto 0) := "1111001";
constant TWELVE_7SEG: std_logic_vector(6 downto 0) := "0100100";
constant THIRTEEN_7SEG: std_logic_vector(6 downto 0) := "0110000";
constant FOURTEEN_7SEG: std_logic_vector(6 downto 0) := "0110001";
constant FIFTEEN_7SEG: std_logic_vector(6 downto 0) := "0010010";
constant SIXTEEN_7SEG: std_logic_vector(6 downto 0) := "0000010";
constant SEVENTEEN_7SEG: std_logic_vector(6 downto 0) := "1111000";
constant EIGHTEEN_7SEG: std_logic_vector(6 downto 0) := "0000000";
constant NINETEEN_7SEG: std_logic_vector(6 downto 0) := "0010000";
constant TWENTY_7SEG: std_logic_vector(6 downto 0) := "1111001";
-------------------led dance-------------------------------------- ` constant step_one: std_logic_vector(15 downto 0):="0000000000000001";`
constant step_two: std_logic_vector(15 downto 0):="0000000000000010";
constant step_three: std_logic_vector(15 downto 0):="0000000000000100";
constant step_four: std_logic_vector(15 downto 0):="0000000000001000";
constant step_five: std_logic_vector(15 downto 0):="0000000000010000";
constant step_six: std_logic_vector(15 downto 0) :="0000000000100000";
constant step_seven: std_logic_vector(15 downto 0) :="0000000001000000";
constant step_eight: std_logic_vector(15 downto 0) :="0000000010000000";
constant step_nine: std_logic_vector(15 downto 0) :="0000000100000000";
constant step_ten: std_logic_vector(15 downto 0) :="0000001000000000";
constant step_eleven: std_logic_vector(15 downto 0):="0000010000000000";
constant step_twelve: std_logic_vector(15 downto 0):="0000100000000000";
constant step_thirteen: std_logic_vector(15 downto 0):="0001000000000000";
constant step_fourteen: std_logic_vector(15 downto 0) :="0010000000000000";
constant step_fifteen: std_logic_vector(15 downto 0) :="0100000000000000";
constant step_sixteen: std_logic_vector(15 downto 0):="1000000000000000";
---------------------active constants-----------------------------------
constant active: std_logic :='1';
constant inactive: std_logic :='0';
constant ACTIVE_RESET: std_logic := '0';
constant TERMINAL_VALUE: integer := 50000000;
-------------------internal connections-------------------------SIGNALS
signal Clock: std_logic;
signal Count: unsigned(7 downto 0);
signal DividedClock: std_logic;
signal Digit0: std_logic_vector(6 downto 0);
signal Digit1: std_logic_vector(6 downto 0);
signal DigitSelect: std_logic;
signal led_dance: std_logic_vector( 15 downto 0);
-----------------clock divider----------------------------
begin
process(Clock)
variable counter: integer range 0 to TERMINAL_VALUE;
begin
if (btnD=ACTIVE_RESET) then
counter := 0;
elsif (rising_edge(Clock)) then
counter := counter + 1;
if (counter = TERMINAL_VALUE) then
counter := 0;
DividedClock <= not DividedClock;
end if;
end if;
end process;
--------------------------counter-----------------------------
process(Clock)
begin
if (btnD=active) then
count <= "00000000";
elsif (rising_edge(Clock)) then
count <= count + 1;
end if;
end process;
-------------------BCD to 7seg--------------------------------
with count select
Digit0 <= ZERO_7SEG when "0000000",
ONE_7SEG when "0000001",
TWO_7SEG when "0000010",
THREE_7SEG when "0000011",
FOUR_7SEG when "0000100",
FIVE_7SEG when "0000101",
SIX_7SEG when "0000110",
SEVEN_7SEG when "0000111",
EIGHT_7SEG when "0001000",
NINE_7SEG when "0001001",
TEN_7SEG when "0001010",
ELEVEN_7SEG when "0001011",
TWELVE_7SEG when "0001100",
THIRTEEN_7SEG when "0001101",
FOURTEEN_7SEG when "0001110",
FIFTEEN_7SEG when "0001111",
SIXTEEN_7SEG when "0010000",
SEVENTEEN_7SEG when "0010001",
EIGHTEEN_7SEG when "0010010",
NINETEEN_7SEG when "0010011",
TWENTY_7SEG when others;
with count select
Digit1 <= ZERO_7SEG when "0000000",
ZERO_7SEG when "0000001",
ZERO_7SEG when "0000010",
ZERO_7SEG when "0000011",
ZERO_7SEG when "0000100",
ZERO_7SEG when "0000101",
ZERO_7SEG when "0000110",
ZERO_7SEG when "0000111",
ZERO_7SEG when "0001000",
ZERO_7SEG when "0001001",
TWO_7SEG when "0010100",
ONE_7SEG when others;
end Behavioral;
IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
使用IEEE.NUMERIC_STD.all；
实体实验室3是
港口（
-------------led输出-------------------------------------
led：输出标准逻辑向量（15至0）；
-------------按钮输入----------------------------------
btnc：标准逻辑中；
btnd：标准逻辑中；
-----------7段输出--------------------------------------------
seg:out标准逻辑向量（从6到0）；--MSB=a:LSB=g
-------------7 seg启用----------------------------------------
an:out标准逻辑向量（3到0）
);
结束实验3；
实验室3的架构是
------十进制七段显示-----------------常数
常数0_7SEG:std_逻辑_向量（6到0）：=“1000000”；
常数1_7SEG:std_逻辑_向量（6到0）：=“1111001”；
常数2_7SEG:std_逻辑_向量（6到0）：=“0100100”；
常数三段：标准逻辑向量（6到0）：=“011000”；
常数四段：标准逻辑向量（6到0）：=“0011001”；
常数五段：标准逻辑向量（6到0）：=“0010010”；
常数六段：标准逻辑向量（6到0）：=“0000010”；
常数SEVEN_7SEG:std_逻辑_向量（6到0）：=“1111000”；
常量八段：标准逻辑向量（6到0）：=“0000000”；
常数九段：标准逻辑向量（6到0）：=“0010000”；
常数TEN_7SEG:std_逻辑_向量（6到0）：=“1000000”；
常数11_7SEG:std_逻辑_向量（6到0）：=“1111001”；
常数12_7SEG:std_逻辑_向量（6到0）：=“0100100”；
常数13_7SEG:std_逻辑_向量（6到0）：=“011000”；
常数14_7SEG:std_逻辑_向量（6到0）：=“011001”；
常数15_7SEG:std_逻辑_向量（6到0）：=“0010010”；
常数16_7SEG:std_逻辑_向量（6到0）：=“0000010”；
常数17_7SEG:std_逻辑_向量（6到0）：=“1111000”；
常数18_7SEG:std_逻辑_向量（6到0）：=“0000000”；
常数19_7SEG:std_逻辑_向量（6到0）：=“0010000”；
常数二十段：标准逻辑向量（6到0）：=“1111001”；
-------------------led舞蹈--------------------`恒定步长第一步：标准逻辑向量（15到0）：=“000000000000000 1”`
常数步长二：标准逻辑向量（15到0）：=“00000000000000 10”；
常数步长三：标准逻辑向量（15到0）：=“00000000000000100”；
常数步长四：标准逻辑向量（15到0）：=“0000000000001000”；
常数步长五：标准逻辑向量（15到0）：=“0000000000010000”；
常数步长六：标准逻辑向量（15到0）：=“0000000000 100000”；
常数步长七：标准逻辑向量（15到0）：=“000000000 1000000”；
常数步长八：标准逻辑向量（15到0）：=“00000000 10000000”；
常量步骤九：标准逻辑向量（15到0）：=“0000000 100000000”；
常数步长：标准逻辑向量（15到0）：=“000000100000000”；
常数步长十一：标准逻辑向量（15到0）：=“000001000000000”；
常数步长：标准逻辑向量（15到0）：=“000010000000”；
常数步进_十三：标准逻辑_向量（15到0）：=“00010000000000”；
常数步长十四：标准逻辑向量（15到0）：=“0010000000000000”；
常数步长_十五：标准逻辑_向量（15向下至0）：=“0100000000000000”；
常数步长十六：标准逻辑向量（15到0）：=“10000000000000”；
---------------------活性常数-----------------------------------
恒定激活：标准逻辑：='1'；
常数不活动：标准逻辑：='0'；
恒定有效_重置：标准_逻辑：='0'；
常数终端_值：整数：=50000000；
-------------------内部连接--------------------信号
信号时钟：标准逻辑；
信号计数：无符号（7到0）；
信号分配锁：标准逻辑；
信号数字0：标准逻辑向量（6到0）；
信号数字1：标准逻辑向量（6到0）；
信号数字选择：标准逻辑；
信号led舞蹈：标准逻辑矢量（15至0）；
-----------------时钟分频器----------------------------
开始
进程（时钟）
变量计数器：从0到终端值的整数范围；
开始
如果（btnD=激活\复位），则
计数器：=0；
elsif（上升沿（时钟））然后
计数器：=计数器+1；
如果（计数器=终端值），则
计数器：=0；
DividedClock有几个设计示例，包括vhdl.us上的SSD。我想您需要将Digit0
或Digit1
信号连接到seg
输出端口
根据我使用此类显示器的经验，我假设所有四位数字都将显示由seg
编码的模式。为了显示每个数字的不同模式，可以使用an
输出快速打开和关闭各个数字，以便在任何给定时刻只有一个数字打开，同时在Digit0
和Digit1
之间切换seg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity lab_3 is
Port (
-------------led output-------------------------------------
led: out std_logic_vector(15 downto 0);
-------------button inputs----------------------------------
btnc: in std_logic;
btnd: in std_logic;
-----------7 seg outpus--------------------------------------------
seg: out std_logic_vector(6 downto 0); --MSB=a: LSB=g
-------------7 seg enables----------------------------------------
an: out std_logic_vector(3 downto 0)
);
end lab_3;
architecture Behavioral of lab_3 is
------decimal seven segment display--------------------------CONSTANTS
constant ZERO_7SEG: std_logic_vector(6 downto 0) := "1000000";
constant ONE_7SEG: std_logic_vector(6 downto 0) := "1111001";
constant TWO_7SEG: std_logic_vector(6 downto 0) := "0100100";
constant THREE_7SEG: std_logic_vector(6 downto 0) := "0110000";
constant FOUR_7SEG: std_logic_vector(6 downto 0) := "0011001";
constant FIVE_7SEG: std_logic_vector(6 downto 0) := "0010010";
constant SIX_7SEG: std_logic_vector(6 downto 0) := "0000010";
constant SEVEN_7SEG: std_logic_vector(6 downto 0) := "1111000";
constant EIGHT_7SEG: std_logic_vector(6 downto 0) := "0000000";
constant NINE_7SEG: std_logic_vector(6 downto 0) := "0010000";
constant TEN_7SEG: std_logic_vector(6 downto 0) := "1000000";
constant ELEVEN_7SEG: std_logic_vector(6 downto 0) := "1111001";
constant TWELVE_7SEG: std_logic_vector(6 downto 0) := "0100100";
constant THIRTEEN_7SEG: std_logic_vector(6 downto 0) := "0110000";
constant FOURTEEN_7SEG: std_logic_vector(6 downto 0) := "0110001";
constant FIFTEEN_7SEG: std_logic_vector(6 downto 0) := "0010010";
constant SIXTEEN_7SEG: std_logic_vector(6 downto 0) := "0000010";
constant SEVENTEEN_7SEG: std_logic_vector(6 downto 0) := "1111000";
constant EIGHTEEN_7SEG: std_logic_vector(6 downto 0) := "0000000";
constant NINETEEN_7SEG: std_logic_vector(6 downto 0) := "0010000";
constant TWENTY_7SEG: std_logic_vector(6 downto 0) := "1111001";
-------------------led dance-------------------------------------- ` constant step_one: std_logic_vector(15 downto 0):="0000000000000001";`
constant step_two: std_logic_vector(15 downto 0):="0000000000000010";
constant step_three: std_logic_vector(15 downto 0):="0000000000000100";
constant step_four: std_logic_vector(15 downto 0):="0000000000001000";
constant step_five: std_logic_vector(15 downto 0):="0000000000010000";
constant step_six: std_logic_vector(15 downto 0) :="0000000000100000";
constant step_seven: std_logic_vector(15 downto 0) :="0000000001000000";
constant step_eight: std_logic_vector(15 downto 0) :="0000000010000000";
constant step_nine: std_logic_vector(15 downto 0) :="0000000100000000";
constant step_ten: std_logic_vector(15 downto 0) :="0000001000000000";
constant step_eleven: std_logic_vector(15 downto 0):="0000010000000000";
constant step_twelve: std_logic_vector(15 downto 0):="0000100000000000";
constant step_thirteen: std_logic_vector(15 downto 0):="0001000000000000";
constant step_fourteen: std_logic_vector(15 downto 0) :="0010000000000000";
constant step_fifteen: std_logic_vector(15 downto 0) :="0100000000000000";
constant step_sixteen: std_logic_vector(15 downto 0):="1000000000000000";
---------------------active constants-----------------------------------
constant active: std_logic :='1';
constant inactive: std_logic :='0';
constant ACTIVE_RESET: std_logic := '0';
constant TERMINAL_VALUE: integer := 50000000;
-------------------internal connections-------------------------SIGNALS
signal Clock: std_logic;
signal Count: unsigned(7 downto 0);
signal DividedClock: std_logic;
signal Digit0: std_logic_vector(6 downto 0);
signal Digit1: std_logic_vector(6 downto 0);
signal DigitSelect: std_logic;
signal led_dance: std_logic_vector( 15 downto 0);
-----------------clock divider----------------------------
begin
process(Clock)
variable counter: integer range 0 to TERMINAL_VALUE;
begin
if (btnD=ACTIVE_RESET) then
counter := 0;
elsif (rising_edge(Clock)) then
counter := counter + 1;
if (counter = TERMINAL_VALUE) then
counter := 0;
DividedClock <= not DividedClock;
end if;
end if;
end process;
--------------------------counter-----------------------------
process(Clock)
begin
if (btnD=active) then
count <= "00000000";
elsif (rising_edge(Clock)) then
count <= count + 1;
end if;
end process;
-------------------BCD to 7seg--------------------------------
with count select
Digit0 <= ZERO_7SEG when "0000000",
ONE_7SEG when "0000001",
TWO_7SEG when "0000010",
THREE_7SEG when "0000011",
FOUR_7SEG when "0000100",
FIVE_7SEG when "0000101",
SIX_7SEG when "0000110",
SEVEN_7SEG when "0000111",
EIGHT_7SEG when "0001000",
NINE_7SEG when "0001001",
TEN_7SEG when "0001010",
ELEVEN_7SEG when "0001011",
TWELVE_7SEG when "0001100",
THIRTEEN_7SEG when "0001101",
FOURTEEN_7SEG when "0001110",
FIFTEEN_7SEG when "0001111",
SIXTEEN_7SEG when "0010000",
SEVENTEEN_7SEG when "0010001",
EIGHTEEN_7SEG when "0010010",
NINETEEN_7SEG when "0010011",
TWENTY_7SEG when others;
with count select
Digit1 <= ZERO_7SEG when "0000000",
ZERO_7SEG when "0000001",
ZERO_7SEG when "0000010",
ZERO_7SEG when "0000011",
ZERO_7SEG when "0000100",
ZERO_7SEG when "0000101",
ZERO_7SEG when "0000110",
ZERO_7SEG when "0000111",
ZERO_7SEG when "0001000",
ZERO_7SEG when "0001001",
TWO_7SEG when "0010100",
ONE_7SEG when others;
end Behavioral;
如果切换速度足够快，眼睛看不清楚。如果是多路复用显示器，则需要多路复用器。