VHDL中的过程返回未知
我必须比较功能代码和rtl代码。以下代码是作为16位输入的两个组件的结构代码编写的。我已尝试对以下电路进行编码: 在此,我附上了代码和测试台:VHDL中的过程返回未知,vhdl,Vhdl,我必须比较功能代码和rtl代码。以下代码是作为16位输入的两个组件的结构代码编写的。我已尝试对以下电路进行编码: 在此,我附上了代码和测试台: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity two_s_complement_16bit_rtl is Port ( A : in STD_LOGIC_VECTOR (15 downto 0); Cout : out STD_LOGIC_VECTOR (15 d
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity two_s_complement_16bit_rtl is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
Cout : out STD_LOGIC_VECTOR (15 downto 0):= (others => '0'));
end two_s_complement_16bit_rtl;
architecture Behavioral of two_s_complement_16bit_rtl is
procedure two_s_complement (
A : in std_logic;
B : in std_logic;
C : out std_logic;
cout : out std_logic;
cin : in std_logic) is
begin
cout := ((not A) and B) xor (((not A) xor B) and cin);
end procedure;
begin
process (A)
variable temp_C, temp_Cout: STD_LOGIC_VECTOR(15 downto 0);
constant B_0 : STD_LOGIC := '1';
constant B_1 : STD_LOGIC := '0';
begin
for i in 0 to 15 loop
if (i = 0) then
two_s_complement ( A(i), B_0 ,temp_C(i) ,temp_Cout(i) , B_1);
else
two_s_complement ( A(i), B_1 ,temp_C(i) ,temp_Cout(i) , temp_C(i-1));
end if;
end loop;
Cout <= temp_Cout;
end process;
end Behavioral;
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity two_s_complement_16bit_rtl_tb is
end;
architecture bench of two_s_complement_16bit_rtl_tb is
component two_s_complement_16bit_rtl
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
Cout : out STD_LOGIC_VECTOR (15 downto 0):= (others => '0'));
end component;
signal A: STD_LOGIC_VECTOR (15 downto 0);
signal Cout: STD_LOGIC_VECTOR (15 downto 0):= (others => '0');
begin
uut: two_s_complement_16bit_rtl port map ( A => A,
Cout => Cout );
stimulus: process
begin
-- Put initialisation code here
A <= "0100010010110000";
wait for 10 ns;
A <= "0011000011110111";
wait for 10 ns;
A <= "0000000000000001";
wait for 10 ns;
A <= "0011110010110011";
wait for 10 ns;
A <= "0010000100100001";
wait for 10 ns;
A <= "0001011100100011";
wait for 10 ns;
A <= "1011000110111001";
wait for 10 ns;
A <= "0000001011001010";
wait for 10 ns;
A <= "0011110110100000";
wait for 10 ns;
A <= "0100000111111000";
wait for 10 ns;
A <= "1011111001111100";
wait for 10 ns;
A <= "1111000110000001";
wait for 10 ns;
A <= "0111000111001011";
wait for 10 ns;
A <= "1011011101101010";
wait for 10 ns;
A <= "1111001001010111";
wait for 10 ns;
-- Put test bench stimulus code here
wait;
end process;
end;
IEEE库;
使用IEEE.STD_LOGIC_1164.ALL;
实体2\u s\u补码\u 16位\u rtl为
端口(A:标准逻辑向量(15到0);
Cout:out标准逻辑向量(15到0):=(其他=>'0');
结束两个\u s\u补码\u 16位\u rtl;
两个s_互补16位rtl的体系结构是
程序二(
答:标准逻辑;
B:标准逻辑;
C:输出标准逻辑;
cout:输出标准逻辑;
cin:在标准逻辑中)是
开始
cout:=((非A)和B)xor((非A)xor B)和cin);
结束程序;
开始
过程(A)
变量温度C,温度系数:标准逻辑向量(15到0);
常数B_0:STD_逻辑:='1';
常数B_1:STD_逻辑:='0';
开始
对于0到15循环中的i
如果(i=0),则
两个补码(A(i),B_0,temp_C(i),temp_Cout(i),B_1);
其他的
两个补码(A(i),B_1,temp_C(i),temp_Cout(i),temp_C(i-1));
如果结束;
端环;
Cout'0');
端部元件;
信号A:标准逻辑向量(15至0);
信号输出:标准逻辑向量(15到0):=(其他=>'0');
开始
uut:two_s_complete_16bit_rtl端口映射(A=>A,
Cout=>Cout);
刺激:过程
开始
--在这里输入初始化代码
A有三个明显的错误
首先,两个s_补码过程不分配C,这很容易修复:
procedure
two_s_complement (
a: in std_logic;
b: in std_logic;
c: out std_logic;
cout: out std_logic;
cin: in std_logic
) is
variable inta: std_logic := not a;
begin
c := inta xor b xor cin; -- ADDED
cout := ((not a) and b) xor (((not a) xor b) and cin);
-- cout := (inta and b) or (inta and cin);
end procedure;
这是一个输入反转的全加器
其次,您在过程调用中与cin的关联不正确:
for i in 0 to 15 loop
if i = 0 then
two_s_complement (
a => a(i),
b => b_0,
c => temp_c(i),
cout => temp_cout(i),
cin => b_1
);
else
two_s_complement (
a => a(i),
b => b_1,
c => temp_c(i),
cout => temp_cout(i),
cin => temp_cout(i - 1) -- WAS temp_c(i-1)
);
end if;
当您使用命名关联时,错误会突出
第三,两个s_补码16位rtl的cout输出应从temp_c分配:
cout <= temp_c; -- WAS temp_cout;
coutreturn(-A)代码>工作完成。正如在文章中所说,我必须将rtl与functional进行比较,这就是我编写此代码的原因。您的循环过程调用没有实现所示的电路。该过程应实现一个全加器,例如,不分配C输出(传播“U”)。在过程调用中还存在错误的位置关联,在使用命名关联时很容易出现。当i/=0时,cin输入应与温度(i-1)相关联。也cout