Vhdl 如何检查像素标准逻辑向量的偶数和奇数
我想知道“我有2个值,它是Vhdl 如何检查像素标准逻辑向量的偶数和奇数,vhdl,Vhdl,我想知道“我有2个值,它是std\u logic\u vector,我想检查它的最后一位是否为奇数和偶数,我想让它们都计算像素值的准确位置。这可以通过case语句实现” 我只想检查LSB。使用case检查两个LSB是: process(x_cont, y_cont) type res_t is (both_low, one_low, none_low); variable result: res_t; variable lsbs: std_logic_vector(1
std\u logic\u vector
,我想检查它的最后一位是否为奇数和偶数,我想让它们都计算像素值的准确位置。这可以通过case语句实现”
我只想检查LSB。使用case检查两个LSB是:
process(x_cont, y_cont)
type res_t is (both_low, one_low, none_low);
variable result: res_t;
variable lsbs: std_logic_vector(1 downto 0);
begin
lsbs:=x_cont(0) & y_cont(0);
case (lsbs) is
when "00" =>
result:=both_low;
when "01" | "10" =>
result:=one_low;
when others =>
result:=none_low;
end case;
end process;
检查lsb很容易:如果x_cont(0)=“1”,则
process(x_cont, y_cont)
type res_t is (both_low, one_low, none_low);
variable result: res_t;
variable lsbs: std_logic_vector(1 downto 0);
begin
lsbs:=x_cont(0) & y_cont(0);
case (lsbs) is
when "00" =>
result:=both_low;
when "01" | "10" =>
result:=one_low;
when others =>
result:=none_low;
end case;
end process;