Vhdl vivado X_接口_信息未显示在块设计gui中
在我的VHDL中，我有一个APB从机的顶级接口和一个AXI主端口，然后我将这些接口标记为Xilinx接口，以便Vivado知道如何在Vivado的Block Designer GUI中将它们组合在一起。代码如下：Vhdl vivado X_接口_信息未显示在块设计gui中,vhdl,fpga,xilinx,vivado,Vhdl,Fpga,Xilinx,Vivado,在我的VHDL中，我有一个APB从机的顶级接口和一个AXI主端口，然后我将这些接口标记为Xilinx接口，以便Vivado知道如何在Vivado的Block Designer GUI中将它们组合在一起。代码如下： library ieee; use ieee.std_logic_1164.all; entity rtl_top is port( -- Clocks axi_aclk :in std_logic; ax
library ieee;
use ieee.std_logic_1164.all;
entity rtl_top is
port(
-- Clocks
axi_aclk :in std_logic;
axi_arst_n :in std_logic;
-- Peripheral Servant Port: from ZYNQ Master Port
-- (Connect to ZYNQ M_AXI_GPO -> axi-interconnect -> axi-apb-bridge)
s_apb_gp0_paddr :in std_logic_vector(31 downto 0);
s_apb_gp0_psel :in std_logic;
s_apb_gp0_penable :in std_logic;
s_apb_gp0_pwrite :in std_logic;
s_apb_gp0_pwdata :in std_logic_vector(31 downto 0);
s_apb_gp0_pready :out std_logic;
s_apb_gp0_prdata :out std_logic_vector(31 downto 0);
s_apb_gp0_pslverr :out std_logic;
--Peripheral DMA port: to ZYNQ Servant Port S_AXI_GP0
-- (actually, don't connect it, its just a placeholder)
m_axi_gp0_araddr :out std_logic_vector(31 downto 0);
m_axi_gp0_arburst :out std_logic_vector(1 downto 0);
m_axi_gp0_arcache :out std_logic_vector(3 downto 0);
m_axi_gp0_arid :out std_logic_vector(5 downto 0);
m_axi_gp0_arlen :out std_logic_vector(3 downto 0);
m_axi_gp0_arlock :out std_logic_vector(1 downto 0);
m_axi_gp0_arprot :out std_logic_vector(2 downto 0);
m_axi_gp0_arqos :out std_logic_vector(3 downto 0);
m_axi_gp0_arready :in std_logic;
m_axi_gp0_arsize :out std_logic_vector(2 downto 0);
m_axi_gp0_arvalid :out std_logic;
m_axi_gp0_awaddr :out std_logic_vector(31 downto 0);
m_axi_gp0_awburst :out std_logic_vector(1 downto 0);
m_axi_gp0_awid :out std_logic_vector(5 downto 0);
m_axi_gp0_awprot :out std_logic_vector(2 downto 0);
m_axi_gp0_awqos :out std_logic_vector(3 downto 0);
m_axi_gp0_awready :in std_logic;
m_axi_gp0_awvalid :out std_logic;
m_axi_gp0_bid :in std_logic_vector(5 downto 0);
m_axi_gp0_bready :out std_logic;
m_axi_gp0_bresp :in std_logic_vector(1 downto 0);
m_axi_gp0_bvalid :in std_logic;
m_axi_gp0_rdata :in std_logic_vector(31 downto 0);
m_axi_gp0_rid :in std_logic_vector(5 downto 0);
m_axi_gp0_rlast :in std_logic;
m_axi_gp0_rready :out std_logic;
m_axi_gp0_rresp :in std_logic_vector(1 downto 0);
m_axi_gp0_rvalid :in std_logic;
m_axi_gp0_wdata :out std_logic_vector(31 downto 0);
m_axi_gp0_wid :out std_logic_vector(5 downto 0);
m_axi_gp0_wlast :out std_logic;
m_axi_gp0_wready :in std_logic;
m_axi_gp0_wstrb :out std_logic_vector(3 downto 0);
m_axi_gp0_wvalid :out std_logic
);
ATTRIBUTE X_INTERFACE_INFO :STRING;
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_paddr :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PADDR";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_psel :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PSEL";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_penable :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PENABLE";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_pwrite :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PWRITE";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_pwdata :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PWDATA";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_pready :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PREADY";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_prdata :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PRDATA";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_pslverr :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PSLVERR";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_araddr :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_arburst :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_arcache :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_arid :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_arlen :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_arlock :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_arprot :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_arqos :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_arready :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_arsize :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_arvalid :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_awaddr :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_awburst :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_awid :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_awprot :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_awqos :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_awready :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_awvalid :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_bid :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_bready :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_bresp :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_bvalid :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_rdata :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_rid :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_rlast :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_rready :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_rresp :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_rvalid :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_wdata :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_wid :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_wlast :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_wready :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_wstrb :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
ATTRIBUTE X_INTERFACE_INFO of m_axi_gp0_wvalid :SIGNAL is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
end entity;
architecture rtl of rtl_top is
begin
--ZYNQ API Slave Port Placeholder
s_apb_gp0_pready <= '0';
s_apb_gp0_prdata <= (others => '0');
s_apb_gp0_pslverr <= '0';
--ZYNQ Axi MASTER Port Placeholder
m_axi_gp0_araddr <= (others => '0');
m_axi_gp0_arburst <= (others => '0');
m_axi_gp0_arcache <= (others => '0');
m_axi_gp0_arid <= (others => '0');
m_axi_gp0_arlen <= (others => '0');
m_axi_gp0_arlock <= (others => '0');
m_axi_gp0_arprot <= (others => '0');
m_axi_gp0_arqos <= (others => '0');
m_axi_gp0_arsize <= (others => '0');
m_axi_gp0_awaddr <= (others => '0');
m_axi_gp0_awburst <= (others => '0');
m_axi_gp0_awid <= (others => '0');
m_axi_gp0_awprot <= (others => '0');
m_axi_gp0_awqos <= (others => '0');
m_axi_gp0_wdata <= (others => '0');
m_axi_gp0_wid <= (others => '0');
m_axi_gp0_wstrb <= (others => '0');
m_axi_gp0_arvalid <= '0';
m_axi_gp0_awvalid <= '0';
m_axi_gp0_bready <= '0';
m_axi_gp0_rready <= '0';
m_axi_gp0_wlast <= '0';
m_axi_gp0_wvalid <= '0';
end architecture;
ieee库；
使用ieee.std_logic_1164.all；
实体rtl_顶部为
港口(
--时钟
axi_aclk：标准逻辑中；
axi_arst_n：标准逻辑中；
--外围服务端口：来自ZYNQ主端口
--（连接到ZYNQ M_AXI_GPO->AXI互连->AXI apb桥接器）
s_apb_gp0_paddr：标准逻辑向量（31到0）；
s_apb_gp0_psel：标准逻辑中；
s_apb_gp0_可处罚：标准逻辑；
s_apb_GP0pwrite：标准逻辑中；
s_apb_gp0_pwdata：标准逻辑向量（31向下至0）；
s_apb_gp0_pready：输出标准逻辑；
s_apb_gp0_prdata：输出标准逻辑向量（31向下至0）；
s_apb_gp0_pslverr：输出标准逻辑；
--外围DMA端口：至ZYNQ服务端口S_AXI_GP0
--（实际上，不要连接它，它只是一个占位符）
m_axi_gp0_araddr：输出标准逻辑向量（31向下至0）；
m_axi_gp0_arburst：输出标准逻辑向量（1到0）；
m_axi_gp0_arcache：输出标准逻辑向量（3到0）；
m_axi_gp0_和：输出标准逻辑向量（5到0）；
m_axi_gp0_arlen：输出标准逻辑向量（3到0）；
m_axi_gp0_arlock：输出标准逻辑向量（1到0）；
m_axi_gp0_arprot：输出标准逻辑向量（2到0）；
m_axi_gp0_arqos：输出标准逻辑向量（3到0）；
m_axi_gp0_arready：标准逻辑中；
m_axi_gp0_arsize：输出标准逻辑向量（2到0）；
m_axi_gp0_arvalid：输出标准逻辑；
m_axi_gp0_awaddr：输出标准逻辑向量（31向下至0）；
m_axi_gp0_awburst：输出标准逻辑向量（1到0）；
m_axi_gp0_awid：输出标准逻辑向量（5到0）；
m_axi_gp0_awprot：输出标准逻辑向量（2到0）；
m_axi_gp0_awqos：输出标准逻辑向量（3到0）；
m_axi_gp0_awready：标准逻辑中；
m_axi_gp0_awvalid：输出标准逻辑；
m_axi_gp0_bid：标准逻辑向量（5到0）；
m_axi_gp0_bready：输出标准逻辑；
m_axi_gp0_bresp：标准逻辑向量（1到0）；
m_axi_GP0bValid：标准逻辑中；
m_axi_gp0rdata：标准逻辑向量（31到0）；
m_axi_gp0_rid：标准逻辑向量（5到0）；
m_axi_GP0rlast：标准逻辑中；
m_axi_gp0_rready：输出标准逻辑；
m_axi_gp0_rresp：标准逻辑向量（1到0）；
m_axi_GP0rvalid：标准逻辑中；
m_axi_gp0_wdata：输出标准逻辑向量（31到0）；
m_axi_gp0_wid：输出标准逻辑向量（5到0）；
m_axi_gp0_wlast：输出标准逻辑；
m_axi_gp0_圈：标准逻辑中；
m_axi_gp0_wstrb：输出标准逻辑向量（3到0）；
m_axi_gp0_wvalid:输出标准逻辑
);
属性X_接口_信息：字符串；
s_apb_gp0_paddr的属性X_接口_信息：信号为“xilinx.com:INTERFACE:apb:1.0 s_apb_gp0 paddr”；
s_apb_gp0_psel的属性X_接口_信息：信号为“xilinx.com:INTERFACE:apb:1.0 s_apb_gp0 psel”；
s_apb_gp0_可处罚属性X_接口_信息：信号为“xilinx.com:接口：apb:1.0 s_apb_gp0可处罚”；
s_apb_gp0_编写的属性X_接口_信息：信号为“xilinx.com:INTERFACE:apb:1.0 s_apb_gp0编写”；
s_apb_gp0_pwdata的属性X_接口_信息：信号为“xilinx.com:INTERFACE:apb:1.0 s_apb_gp0 pwdata”；
s_apb_gp0_pready的属性X_接口_信息：信号为“xilinx.com:接口：apb:1.0 s_apb_gp0 pready”；
s_apb_gp0_prdata的属性X_接口_信息：信号为“xilinx.com:接口：apb:1.0 s_apb_gp0 prdata”；
s_apb_gp0_pslverr的属性X_接口_信息：信号为“xilinx.com:INTERFACE:apb:1.0 s_apb_gp0 pslverr”；
m_axi_gp0_araddr的属性X_INTERFACE_INFO:信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 araddr”；
m_axi_gp0_arburst的属性X_接口信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 arburst”；
m_axi_gp0_arcache的属性X_INTERFACE_信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 arcache”；
m_axi_gp0_和属性X_接口信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0和”；
m_axi_gp0_arlen的属性X_INTERFACE_信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 arlen”；
m_axi_gp0_arlock的属性X_INTERFACE_信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 arlock”；
m_axi_gp0_arprot的属性X_INTERFACE_信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 arprot”；
m_axi_gp0_arqos的属性X_接口信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 arqos”；
m_axi_gp0_Arrady的属性X_接口信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 Arrady”；
m_axi_gp0_arsize的属性X_INTERFACE_信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 arsize”；
m_axi_gp0_arvalid的属性X_INTERFACE_信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 arvalid”；
m_axi_gp0_awaddr的属性X_INTERFACE_INFO:信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 awaddr”；
m_axi_gp0_awburst的属性X_接口信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 awburst”；
m_axi_gp0_awid的属性X_接口信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 awid”；
m_axi_gp0_awprot的属性X_接口信息：信号为“xilinx.com:INTERFACE:aximm:1.0 m_axi_gp0 awprot”；
ATT
library ieee;
use ieee.std_logic_1164.all;
entity rtl_top is
port(
-- Clocks
axi_aclk :in std_logic;
axi_arst_n :in std_logic;
-- Peripheral Servant Port: from ZYNQ Master Port
-- (Connect to ZYNQ M_AXI_GPO -> axi-interconnect -> axi-apb-bridge)
s_apb_gp0_paddr :in std_logic_vector(31 downto 0);
s_apb_gp0_psel :in std_logic;
s_apb_gp0_penable :in std_logic;
s_apb_gp0_pwrite :in std_logic;
s_apb_gp0_pwdata :in std_logic_vector(31 downto 0);
s_apb_gp0_pready :out std_logic;
s_apb_gp0_prdata :out std_logic_vector(31 downto 0);
s_apb_gp0_pslverr :out std_logic;
--Peripheral DMA port: to ZYNQ Servant Port S_AXI_GP0
-- (actually, don't connect it, its just a placeholder)
m_axi_gp0_araddr :out std_logic_vector(31 downto 0);
m_axi_gp0_arburst :out std_logic_vector(1 downto 0);
m_axi_gp0_arcache :out std_logic_vector(3 downto 0);
m_axi_gp0_arid :out std_logic_vector(5 downto 0);
m_axi_gp0_arlen :out std_logic_vector(3 downto 0);
m_axi_gp0_arlock :out std_logic_vector(1 downto 0);
m_axi_gp0_arprot :out std_logic_vector(2 downto 0);
m_axi_gp0_arqos :out std_logic_vector(3 downto 0);
m_axi_gp0_arready :in std_logic;
m_axi_gp0_arsize :out std_logic_vector(2 downto 0);
m_axi_gp0_arvalid :out std_logic;
m_axi_gp0_awaddr :out std_logic_vector(31 downto 0);
m_axi_gp0_awburst :out std_logic_vector(1 downto 0);
m_axi_gp0_awid :out std_logic_vector(5 downto 0);
m_axi_gp0_awprot :out std_logic_vector(2 downto 0);
m_axi_gp0_awqos :out std_logic_vector(3 downto 0);
m_axi_gp0_awready :in std_logic;
m_axi_gp0_awvalid :out std_logic;
m_axi_gp0_bid :in std_logic_vector(5 downto 0);
m_axi_gp0_bready :out std_logic;
m_axi_gp0_bresp :in std_logic_vector(1 downto 0);
m_axi_gp0_bvalid :in std_logic;
m_axi_gp0_rdata :in std_logic_vector(31 downto 0);
m_axi_gp0_rid :in std_logic_vector(5 downto 0);
m_axi_gp0_rlast :in std_logic;
m_axi_gp0_rready :out std_logic;
m_axi_gp0_rresp :in std_logic_vector(1 downto 0);
m_axi_gp0_rvalid :in std_logic;
m_axi_gp0_wdata :out std_logic_vector(31 downto 0);
m_axi_gp0_wid :out std_logic_vector(5 downto 0);
m_axi_gp0_wlast :out std_logic;
m_axi_gp0_wready :in std_logic;
m_axi_gp0_wstrb :out std_logic_vector(3 downto 0);
m_axi_gp0_wvalid :out std_logic
);
ATTRIBUTE X_INTERFACE_INFO :STRING;
end entity;
architecture rtl of rtl_top is
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_paddr :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PADDR";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_psel :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PSEL";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_penable :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PENABLE";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_pwrite :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PWRITE";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_pwdata :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PWDATA";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_pready :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PREADY";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_prdata :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PRDATA";
ATTRIBUTE X_INTERFACE_INFO of s_apb_gp0_pslverr :SIGNAL is "xilinx.com:interface:apb:1.0 S_APB_GP0 PSLVERR";
begin
--ZYNQ API Slave Port Placeholder
s_apb_gp0_pready <= '0';
s_apb_gp0_prdata <= (others => '0');
s_apb_gp0_pslverr <= '0';
--ZYNQ Axi MASTER Port Placeholder
m_axi_gp0_araddr <= (others => '0');
m_axi_gp0_arburst <= (others => '0');
m_axi_gp0_arcache <= (others => '0');
m_axi_gp0_arid <= (others => '0');
m_axi_gp0_arlen <= (others => '0');
m_axi_gp0_arlock <= (others => '0');
m_axi_gp0_arprot <= (others => '0');
m_axi_gp0_arqos <= (others => '0');
m_axi_gp0_arsize <= (others => '0');
m_axi_gp0_awaddr <= (others => '0');
m_axi_gp0_awburst <= (others => '0');
m_axi_gp0_awid <= (others => '0');
m_axi_gp0_awprot <= (others => '0');
m_axi_gp0_awqos <= (others => '0');
m_axi_gp0_wdata <= (others => '0');
m_axi_gp0_wid <= (others => '0');
m_axi_gp0_wstrb <= (others => '0');
m_axi_gp0_arvalid <= '0';
m_axi_gp0_awvalid <= '0';
m_axi_gp0_bready <= '0';
m_axi_gp0_rready <= '0';
m_axi_gp0_wlast <= '0';
m_axi_gp0_wvalid <= '0';
end architecture;