Vhdl lattice Synthesis引擎编译md5实体时内存不足

我正在编写一个md5哈希函数，在使用Lattice的合成引擎（LSE）合成设计时遇到了一个意想不到的问题。如果有必要的话，合成成MachXO2 7000HE

当我试图合成这个部分计算单个512位输入的md5的实体时，会出现“内存不足”错误。它在使用大约6.6GB的ram很长时间（许多分钟）后停止

我怀疑我可能在这里做了一些非常愚蠢的事情

library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity md5_block is
port(
    clock: in std_logic;
    reset: in std_logic;
    din: in std_logic_vector(511 downto 0);
    dout: out std_logic_vector(127 downto 0));
end entity md5_block;

architecture behavior of md5_block is
type reg_single is array (0 to 15) of std_logic_vector(31 downto 0);
type reg_quad is array (0 to 63) of std_logic_vector(31 downto 0);
type shift_quad is array (0 to 63) of std_logic_vector(4 downto 0);

constant shift_amount: shift_quad := (
    "00111", "01100", "10001", "10110", "00111", "01100", "10001", "10110", 
    "00111", "01100", "10001", "10110", "00111", "01100", "10001", "10110", 
    "00101", "01001", "01110", "10100", "00101", "01001", "01110", "10100",
    "00101", "01001", "01110", "10100", "00101", "01001", "01110", "10100",
    "00100", "01011", "10000", "10111", "00100", "01011", "10000", "10111",
    "00100", "01011", "10000", "10111", "00100", "01011", "10000", "10111",
    "00110", "01010", "01111", "10101", "00110", "01010", "01111", "10101",
    "00110", "01010", "01111", "10101", "00110", "01010", "01111", "10101");

constant k_data: reg_quad := (
     x"d76aa478", x"e8c7b756", x"242070db", x"c1bdceee", x"f57c0faf", x"4787c62a", x"a8304613", x"fd469501",
     x"698098d8", x"8b44f7af", x"ffff5bb1", x"895cd7be", x"6b901122", x"fd987193", x"a679438e", x"49b40821",
     x"f61e2562", x"c040b340", x"265e5a51", x"e9b6c7aa", x"d62f105d", x"02441453", x"d8a1e681", x"e7d3fbc8",
     x"21e1cde6", x"c33707d6", x"f4d50d87", x"455a14ed", x"a9e3e905", x"fcefa3f8", x"676f02d9", x"8d2a4c8a",
     x"fffa3942", x"8771f681", x"6d9d6122", x"fde5380c", x"a4beea44", x"4bdecfa9", x"f6bb4b60", x"bebfbc70",
     x"289b7ec6", x"eaa127fa", x"d4ef3085", x"04881d05", x"d9d4d039", x"e6db99e5", x"1fa27cf8", x"c4ac5665",
     x"f4292244", x"432aff97", x"ab9423a7", x"fc93a039", x"655b59c3", x"8f0ccc92", x"ffeff47d", x"85845dd1",
     x"6fa87e4f", x"fe2ce6e0", x"a3014314", x"4e0811a1", x"f7537e82", x"bd3af235", x"2ad7d2bb", x"eb86d391" );

signal in_data: reg_single;

signal internal_a: std_logic_vector(31 downto 0);
signal internal_b: std_logic_vector(31 downto 0);
signal internal_c: std_logic_vector(31 downto 0);
signal internal_d: std_logic_vector(31 downto 0);

signal message_in: std_logic_vector(31 downto 0);
signal result_f: std_logic_vector(31 downto 0);
signal result_g: std_logic_vector(31 downto 0);
signal result_h: std_logic_vector(31 downto 0);
signal result_i: std_logic_vector(31 downto 0);
signal used_result: std_logic_vector(31 downto 0);

signal pre_add: std_logic_vector(31 downto 0);
signal post_add: std_logic_vector(31 downto 0);
signal post_shift: std_logic_vector(31 downto 0);

signal round_num: std_logic_vector(5 downto 0);
begin
result_f <= (internal_b and internal_c) or (not internal_b and internal_d);
result_g <= (internal_b and internal_d) or (internal_c and not internal_d);
result_h <= internal_b xor internal_c xor internal_d;
result_i <= internal_c xor (internal_b or not internal_d);

in_data(00) <= din(31 downto 0);
in_data(01) <= din(63 downto 32);
in_data(02) <= din(95 downto 64);
in_data(03) <= din(127 downto 96);
in_data(04) <= din(159 downto 128);
in_data(05) <= din(191 downto 160);
in_data(06) <= din(223 downto 192);
in_data(07) <= din(255 downto 224);
in_data(08) <= din(287 downto 256);
in_data(09) <= din(319 downto 288);
in_data(10) <= din(351 downto 320);
in_data(11) <= din(383 downto 352);
in_data(12) <= din(415 downto 384);
in_data(13) <= din(447 downto 416);
in_data(14) <= din(479 downto 448);
in_data(15) <= din(511 downto 480);
message_in <= in_data(to_integer(unsigned(round_num)));

--64 rounds to calculate 128 bit result
--process 512 bits at a time
--32 bits each round
process (all)
begin
    if reset='1' then
        round_num <= (others => '0');
        dout <= (others => '0');
        post_shift <= (others => '0');
        pre_add <= (others => '0');
        post_add <= (others => '0');
        internal_a <= x"67452301";
        internal_b <= x"efcdab89";
        internal_c <= x"98badcfe";
        internal_d <= x"10325476";
    else            
        case round_num(5 downto 4) is
            when "00" => used_result <= result_f;
            when "01" => used_result <= result_g;
            when "10" => used_result <= result_h;
            when "11" => used_result <= result_i;
            when others => used_result <= result_f;
        end case;
        pre_add <= std_logic_vector(unsigned(used_result) + unsigned(internal_a));
        post_add <= std_logic_vector(unsigned(pre_add) + unsigned(message_in) + unsigned(k_data(to_integer(unsigned(round_num)))));
        case shift_amount(to_integer(unsigned(round_num))) is
            when "00000" => post_shift <= post_add;
            when "00001" => post_shift <= post_add(30 downto 0) & post_add(31);
            when "00010" => post_shift <= post_add(29 downto 0) & post_add(31 downto 30);
            when "00011" => post_shift <= post_add(28 downto 0) & post_add(31 downto 29);
            when "00100" => post_shift <= post_add(27 downto 0) & post_add(31 downto 28);
            when "00101" => post_shift <= post_add(26 downto 0) & post_add(31 downto 27);
            when "00110" => post_shift <= post_add(25 downto 0) & post_add(31 downto 26);
            when "00111" => post_shift <= post_add(24 downto 0) & post_add(31 downto 25);
            when "01000" => post_shift <= post_add(23 downto 0) & post_add(31 downto 24);
            when "01001" => post_shift <= post_add(22 downto 0) & post_add(31 downto 23);
            when "01010" => post_shift <= post_add(21 downto 0) & post_add(31 downto 22);
            when "01011" => post_shift <= post_add(20 downto 0) & post_add(31 downto 21);
            when "01100" => post_shift <= post_add(19 downto 0) & post_add(31 downto 20);
            when "01101" => post_shift <= post_add(18 downto 0) & post_add(31 downto 19);
            when "01110" => post_shift <= post_add(17 downto 0) & post_add(31 downto 18);
            when "01111" => post_shift <= post_add(16 downto 0) & post_add(31 downto 17);
            when "10000" => post_shift <= post_add(15 downto 0) & post_add(31 downto 16);
            when "10001" => post_shift <= post_add(14 downto 0) & post_add(31 downto 15);
            when "10010" => post_shift <= post_add(13 downto 0) & post_add(31 downto 14);
            when "10011" => post_shift <= post_add(12 downto 0) & post_add(31 downto 13);
            when "10100" => post_shift <= post_add(11 downto 0) & post_add(31 downto 12);
            when "10101" => post_shift <= post_add(10 downto 0) & post_add(31 downto 11);
            when "10110" => post_shift <= post_add(09 downto 0) & post_add(31 downto 10);
            when "10111" => post_shift <= post_add(08 downto 0) & post_add(31 downto 09);
            when "11000" => post_shift <= post_add(07 downto 0) & post_add(31 downto 08);
            when "11001" => post_shift <= post_add(06 downto 0) & post_add(31 downto 07);
            when "11010" => post_shift <= post_add(05 downto 0) & post_add(31 downto 06);
            when "11011" => post_shift <= post_add(04 downto 0) & post_add(31 downto 05);
            when "11100" => post_shift <= post_add(03 downto 0) & post_add(31 downto 04);
            when "11101" => post_shift <= post_add(02 downto 0) & post_add(31 downto 03);
            when "11110" => post_shift <= post_add(01 downto 0) & post_add(31 downto 02);
            when "11111" => post_shift <= post_add(0) & post_add(31 downto 01);
            when others => post_shift <= post_add;
        end case;
        if rising_edge(clock) then
            round_num <= std_logic_vector(unsigned(round_num) + "00001");
            internal_d <= internal_c;
                internal_c <= internal_b;
                internal_a <= internal_d;
                internal_b <= std_logic_vector(unsigned(post_shift) + unsigned(internal_b));
                dout <= result_f & result_g & result_h & result_i;
            end if;
        end if;
    end process;
end behavior;

ieee库；
使用ieee.std_logic_1164.all；
使用ieee.numeric_std.all；
实体md5_块为
港口(
时钟：标准逻辑；
复位：在标准逻辑中；
din：标准逻辑向量（511到0）；
dout:out标准逻辑向量（127向下到0）；
端实体md5_块；
md5_块的体系结构行为是
类型reg_single是标准逻辑向量（31到0）的数组（0到15）；
reg_quad类型是标准逻辑向量（31到0）的数组（0到63）；
shift_quad类型是标准_逻辑_向量（4到0）的数组（0到63）；
固定移位量：移位四元组=(
"00111", "01100", "10001", "10110", "00111", "01100", "10001", "10110", 
"00111", "01100", "10001", "10110", "00111", "01100", "10001", "10110", 
"00101", "01001", "01110", "10100", "00101", "01001", "01110", "10100",
"00101", "01001", "01110", "10100", "00101", "01001", "01110", "10100",
"00100", "01011", "10000", "10111", "00100", "01011", "10000", "10111",
"00100", "01011", "10000", "10111", "00100", "01011", "10000", "10111",
"00110", "01010", "01111", "10101", "00110", "01010", "01111", "10101",
"00110", "01010", "01111", "10101", "00110", "01010", "01111", "10101");
常数k_数据：reg_quad:=(
x“d76aa478”，x“e8c7b756”，x“242070db”，x“c1bdceee”，x“f57c0faf”，x“4787c62a”，x“a8304613”，x“fd469501”，
x“698098d8”，x“8b44f7af”，x“ffff5bb1”，x“895cd7be”，x“6b901122”，x“fd987193”，x“a679438e”，x“49b40821”，
x“f61e2562”、x“c040b340”、x“265e5a51”、x“e9b6c7aa”、x“d62f105d”、x“02441453”、x“d8a1e681”、x“e7d3fbc8”，
x“21e1cde6”、x“c33707d6”、x“f4d50d87”、x“455a14ed”、x“a9e3e905”、x“fcefa3f8”、x“676f02d9”、x“8d2a4c8a”，
x“fffa3942”、x“8771f681”、x“6d9d6122”、x“fde5380c”、x“a4beea44”、x“4bdecfa9”、x“f6bb4b60”、x“bebfbc70”，
x“289b7ec6”、x“eaa127fa”、x“d4ef3085”、x“04881d05”、x“d9d4d039”、x“e6db99e5”、x“1fa27cf8”、x“c4ac5665”，
x“f4292244”、x“432AF97”、x“ab9423a7”、x“fc93a039”、x“655b59c3”、x“8f0ccc92”、x“FFEF47D”、x“85845dd1”，
x“6fa87e4f”、x“fe2ce6e0”、x“a3014314”、x“4e0811a1”、x“f7537e82”、x“bd3af235”、x“2ad7d2bb”、x“eb86d391”）；
信号输入数据：reg_单；
信号内部_a:std_逻辑_向量（31向下至0）；
信号内部_b:std_逻辑_向量（31向下至0）；
信号内部c：标准逻辑向量（31到0）；
信号内部：标准逻辑向量（31到0）；
信号信息输入：标准逻辑向量（31至0）；
信号结果：标准逻辑向量（31到0）；
信号结果：标准逻辑向量（31到0）；
信号结果：标准逻辑向量（31到0）；
信号结果i：标准逻辑向量（31向下至0）；
使用的信号结果：标准逻辑向量（31到0）；
信号预加：标准逻辑向量（31向下至0）；
信号后加：标准逻辑向量（31至0）；
信号后移位：标准逻辑向量（31向下至0）；
信号轮数：标准逻辑向量（5到0）；
开始
结果_fhmm，Xilinx Vivado在20秒内详细阐述了您的代码。。。它可以是晶格合成的东西。您的代码是VHDL-2008，所以lattice可能不支持这一点？p、 你的代码中有很多东西本来可以写得更简单。使用整数等，但如果它工作，它的工作…感谢有关xilinx vivaldo工作的信息。我觉得有更有效的方法来编码这个。我会及时修改的。嗯，Xilinx Vivado在20秒内完成了你的代码。。。它可以是晶格合成的东西。您的代码是VHDL-2008，所以lattice可能不支持这一点？p、 你的代码中有很多东西本来可以写得更简单。使用整数等，但如果它工作，它的工作…感谢有关xilinx vivaldo工作的信息。我觉得有更有效的方法来编码这个。我会及时修改的。