Vhdl “With Select”块中的条件赋值

是否可以从“with select”块中向信号添加条件ASignment。例如

with state select
    Data <= x"00" when IDLE,
            (x"01" when Count = 0 else x"10") when DATA,
            x"FF" when others;

这不会编译，但是否可以在此块中包含第二个变量？

简短的回答是否

你可以这样做

  process (Count, state)
    variable countData : std_logic_vector (7 downto 0);
  begin
    if Count = 0 then
      countData := x"01";
    else
      countData := x"10";
    end if;
    case state is
      when IDLE   => Data <= x"00";
      when DATA   => Data <= countData;
      when others => Data <= x"FF";
    end case;
  end process;

简而言之，答案是否定的

你可以这样做

  process (Count, state)
    variable countData : std_logic_vector (7 downto 0);
  begin
    if Count = 0 then
      countData := x"01";
    else
      countData := x"10";
    end if;
    case state is
      when IDLE   => Data <= x"00";
      when DATA   => Data <= countData;
      when others => Data <= x"FF";
    end case;
  end process;