Vhdl 位向量和位数组之间的差异

我开始为大学考试学习VHDL，我有一个问题：如前所述，位向量类型和位数组之间的区别是什么

bit_向量是一维数组类型，元素为bit类型。位向量类型在标准包中预定义。 语法：

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只要做一个简单的谷歌搜索，你就会找到答案。谢谢。那么，一个位数组和一个位向量是一样的吗？谢谢。我现在明白了。

type bit_vector is array (natural range <>) of bit; 

entity e is end entity;
architecture a of e is
    signal s1 : bit_vector(0 downto 0);
    type own_bit_vector is array(natural range <>) of bit;
    signal s2 : own_bit_vector(0 downto 0);
begin
    -- next line doesn't work
    --s2 <= s1;
    -- "Error: D:/Hdl/BitVector/BitVector.vhd(7):
    --   Signal "s1" is type std.STANDARD.BIT_VECTOR;
    --   expecting type own_bit_vector."

    -- but this is allowed
    process(s1) begin
        for i in s1'range loop
            s2(i) <= s1(i);
        end loop;
    end process;
end architecture;