vhdl编码中hdl编译器错误的解决
不熟悉vhdl，不知道如何解决在尝试运行Synthesis时遇到的这些错误 hdlcompiler 37:此表达式中不能使用unsigned hdlcompiler 1731:=无法确定确切的重载匹配定义 hdlcompiler 303:字符“2”不在std\U逻辑类型中 任何关于代码示例的建议都会大有帮助vhdl编码中hdl编译器错误的解决,vhdl,Vhdl,不熟悉vhdl，不知道如何解决在尝试运行Synthesis时遇到的这些错误 hdlcompiler 37:此表达式中不能使用unsigned hdlcompiler 1731:=无法确定确切的重载匹配定义 hdlcompiler 303:字符“2”不在std\U逻辑类型中 任何关于代码示例的建议都会大有帮助 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity acqeng is
Port (
Mclk : in STD_LOGIC;
Rst : in STD_LOGIC;
Sclk : in STD_LOGIC;
SDI : in STD_LOGIC;
SDO : out STD_LOGIC;
CS : in STD_LOGIC_VECTOR(1 downto 0);
Int : out STD_LOGIC;
ADC_LRCK : out STD_LOGIC;
ADC_BCK : out STD_LOGIC;
ADC_Data : in STD_LOGIC;
ADC_CS : out STD_LOGIC;
nvSRAM_CS : out STD_LOGIC;
ENG_Sck : out STD_LOGIC;
ENG_SI : in STD_LOGIC;
ENG_SO : out STD_LOGIC;
LaserHiLow : out STD_LOGIC
);
end acqeng;
architecture Behavioral of acqeng is
signal seqcount : unsigned(10 downto 0) := "00000000000";
signal Eng_Sck_en : STD_LOGIC := '0';
signal clkdiv2: STD_LOGIC :='0';
signal Eng_State: STD_LOGIC_VECTOR(2 downto 0) := "000";
CONSTANT IDLE : std_logic_vector(2 downto 0 ) :="000";
CONSTANT OUTPUT_SRAM_HEADER: std_logic_vector(2 downto 0 ) :="001";
CONSTANT SET_LRCK_HIGH:std_logic_vector(2 downto 0 ) :="010";
CONSTANT CLEAR_LRCK_HIGH: std_logic_vector(2 downto 0 ) :="011";
CONSTANT GET_CHANNEL_DATA: std_logic_vector(2 downto 0 ) :="100";
CONSTANT WAIT_FOR_SAMPLE:std_logic_vector(2 downto 0 ) :="101";
CONSTANT CHECK_SAMPLE_COUNT: std_logic_vector(2 downto 0 ) :="110";
CONSTANT CHECK_FOR_IDLE: std_logic_vector(2 downto 0 ) :="111";
signal CycleCnt: unsigned(10 downto 0):="11111111111";
signal SPIbitCnt: unsigned(2 downto 0):= "000";
signal InputReg: std_logic_vector(7 downto 0):= "00000000";
signal NewInput: STD_LOGIC :='0';
signal Run: STD_LOGIC :='0';
CONSTANT DE_SELECT: std_logic_vector(1 downto 0) := "11";
CONSTANT ADC_CS_LOW: std_logic_vector(1 downto 0) := "00";
CONSTANT nvSRAM1_CS_LOW: std_logic_vector(1 downto 0) := "01";
CONSTANT CPLD_SELECT: std_logic_vector(1 downto 0) := "10";
begin
ClkDivseq : process(Mclk,Rst)
begin
if Rst ='0' then
clkdiv2 <= '0';
elsif Mclk ='0' and Mclk'event then
clkdiv2 <= not(clkdiv2);
end if;
end process;
SPILatchseq : process(Sclk, CS, SDI)
begin
if CS /= CPLD_SELECT then
SPIbitCnt <="111";
NewInput <='0';
elsif Sclk ='0' and Sclk'event then
InputReg <= InputReg(6 downto 0)& SDI;
if SPIbitCnt = (unsigned*("000")) then
NewInput <='1';
else
SPIbitCnt <=SPIbitCnt-'1';
end if;
end if;
end process;
AcqEngseq: process(clkdiv2, Rst, CS, NewInput, InputReg)
begin
if Rst= '0' then
Eng_State <=IDLE;
LaserHiLow <='0';
ADC_LRCK <='0';
Eng_Sck_en<='0';
Int<='0';
seqcount<= "00000000000";
elsif clkdiv2 ='0' and clkdiv2'event then
seqcount <= seqcount +'1';
case Eng_State is
when IDLE =>
int <='0';
if NewInput ='1' then
Run <= InputReg(7);
CycleCnt <= unsigned*(InputReg(6 downto 0)&"1111");
end if;
if Run ='1' then
Eng_state <= OUTPUT_SRAM_HEADER;
Eng_Sck_En<='1';
seqcount<= "00000000000";
end if;
when OUTPUT_SRAM_HEADER =>
if seqcount(6 downto 0)= unsigned*("1000000") then
Eng_Sck_En<='0';
Eng_State<= SET_LRCK_HIGH;
seqcount <= "00000000000";
end if;
when SET_LRCK_HIGH =>
if seqcount( 6 downto 0) = unsigned*("0000001") then
ADC_LRCK <='1';
LaserHiLow <= not seqcount(10);
Eng_State<=CLEAR_LRCK_HIGH;
end if ;
when CLEAR_LRCK_HIGH =>
Eng_State<= GET_CHANNEL_DATA;
when GET_CHANNEL_DATA =>
ADC_LRCK <='0';
Eng_Sck_En <='1';
Eng_State <= WAIT_FOR_SAMPLE;
when WAIT_FOR_SAMPLE=>
if seqcount (6 downto 0)= unsigned*("1000011")then
Eng_Sck_En <='0';
Eng_State <= CHECK_SAMPLE_COUNT;
end if;
when CHECK_SAMPLE_COUNT =>
if seqcount( 10 downto 7) = unsigned*("1111") then
Eng_State <= CHECK_FOR_IDLE;
else
Eng_State<= SET_LRCK_HIGH;
end if;
when CHECK_FOR_IDLE=>
if CycleCnt= unsigned*("00000000000") then
Run <='0';
Eng_State <= IDLE;
Int <='1';
else
CycleCnt <= CycleCnt -'1';
Eng_State <= SET_LRCK_HIGH;
end if;
when OTHERS =>
end case;
end if;
end process;
--eng spi bus
ENG_Sck <=(seqcount(0) and Eng_Sck_En) when Run ='1' else Sclk;
ENG_SO <='1' when ( Eng_State = OUTPUT_SRAM_HEADER and
(seqcount(5 downto 0 ) = unsigned*("001011") or
seqcount( 5 downto 0) = unsigned*("001100")))
else '0' when( EngState = OUTPUT_SRAM_HEADER)
else ADC_Data when run ='1'; else SDI;
nvSRAM_CS <='0'; when (Run ='1' or CS = nvSRAM1_CS_LOW) else '1';
ADC_CS <='0'; when ( CS= ADC_CS_LOW and Run= '0') else '1';
--SDO is either SDo or Eng_SI
SDO <= ENG_SI when CS(1) ='0' else Run when CS = CPLD_SELECT '2';
ADC_BCK <= seqcount(0);
end Behavioral;
testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.all;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT <component name>
PORT(
Mclk : in STD_LOGIC;
Rst : in STD_LOGIC;
Sclk : in STD_LOGIC;
SDI : in STD_LOGIC;
SDO : out STD_LOGIC;
CS : in STD_LOGIC_VECTOR(1 downto 0);
Int : out STD_LOGIC;
ADC_LRCK : out STD_LOGIC;
ADC_BCK : out STD_LOGIC;
ADC_Data : in STD_LOGIC;
ADC_CS : out STD_LOGIC;
nvSRAM_CS : out STD_LOGIC;
ENG_Sck : out STD_LOGIC;
ENG_SI : in STD_LOGIC;
ENG_SO : out STD_LOGIC;
LaserHiLow : out STD_LOGIC;
);
END COMPONENT;
signal Mclk : std_logic :='0';
signal Rst : std_logic :='0';
signal Sclk : std_logic :='0';
signal SDI : std_logic :='0';
signal CS : std_logic_vector(1 downto 0) := ( others =>'0');
signal ADC_Data : std_logic :='0';
signal ENG_SI : std_logic :='0';
signal SDO : std_logic;
signal Int : std_logic;
signal ADC_LRCK : std_logic;
signal ADC_BCK : std_logic;
signal ADC_CS : std_logic;
signal nvSRAM_CS : std_logic;
signal ENG_sck : std_logic;
signal ENG_SO : std_logic;
signal LaserHiLow : std_logic;
constant Mclk_period: time := 1 us;
constant Sclk_period: time := 1 us;
BEGIN
uut: acqeng PORT MAP(
Mclk => Mclk,
Rst => Rst,
Sclk => Sclk,
SDI => SDI,
SDO => SDO,
CS => CS,
Int => Int,
ADC_LRCK => ADC_LRCK,
ADC_BCK => ADC_BCK,
ADC_Data => ADC_Data,
ADC_CS => ADC_CS,
nvSRAM_CS => nvSRAM_CS,
ENG_Sck =>ENG_Sck,
ENG_SI =>ENG_SI,
ENG_SO =>ENG_SO,
LaserHiLow => LaserHiLow
);
Mclk_process : process
begin
Mclk <='0';
wait for Mclk_period/2;
Mclk <='1';
wait for Mclk_period/2;
end process;
Sclk_process:process
begin
Sclk <='0';
wait for Sclk_period/2;
Sclk <='1';
wait for Sclk_period/2;
end process
stim_proc : process
begin
wait for 100ms
wait for Mclk_period*10;
wait;
end process;
END;
if SPIbitCnt = (unsigned*("000")) then
if SPIbitCnt = 0 then
这是最好的。使用数字标准库代替非标准库；它重载了unsigned和natural之间的比较，这使它能够工作。在您识别的其他行中有多个类似的错误。建议。识别第37、303和1731行并理解错误消息的含义。我们不能为你这样做；代码中没有1731行是为了开始而发布的。但最后一个错误很明显：std_逻辑表示一个位，它可以是“0”或“1”。因此，不要尝试将其设置为“2”，否则将不起作用。错误表示我无法使用此特定表达式。我需要帮助，因为我不确定我可以使用什么其他表达式。您仍然没有确定错误所指的行，甚至没有确定错误所指的实体。我不知道您所指的是哪个表达式。除非你从根本上改进这个问题，否则你是不可能在这里得到帮助的。首先，制作一个简单的示例，并用完整的错误消息和正确的行号具体询问错误。在您的示例中，我们不会计算行数！您需要在问题中识别并标记这些行。请更正你的缩进。正如错误消息已经告诉您的，“2”不是位值std_逻辑的一部分。进一步说明：使用枚举类型来表示状态，而不是常量。“2”之前缺少一个else。不要使用像1000011这样的神奇数字。切勿使用STD_LOGIC_ARITH和STD_LOGIC_UNSIGNED软件包。这是无效的VHDL:未签名*1000000。你是说一个限定表达式吗？您的设计不应使用异步重置。为什么您的设计工作在下降沿？否则adc_数据在运行时为='1'；else-sdi；分号排除了其他字符的位置。sdo