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Vhdl 整数类型的测试台文件_Vhdl - Fatal编程技术网

Vhdl 整数类型的测试台文件

Vhdl 整数类型的测试台文件,vhdl,Vhdl,我试图在XIlinx ISE 14.7中模拟以下VHDL模块,但生成的VHDL测试台文件假定所有输入和输出端口都是std_逻辑和std_逻辑向量类型 package newtype is type row_t is array(0 to 2) of integer; end newtype; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.newtype.all; entity mymodule is port (indata : in

我试图在XIlinx ISE 14.7中模拟以下VHDL模块,但生成的VHDL测试台文件假定所有输入和输出端口都是std_逻辑和std_逻辑向量类型

package newtype is
type row_t is array(0 to 2) of integer;
end newtype;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.newtype.all;

entity mymodule is
port (indata : in  row_t;
        sum : out integer);
end mymodule;

architecture Behavioral of mymodule is
begin
process (indata)
begin
    sum <= indata(0) + indata(1) + indata(2);
end process;
end Behavioral;
我修改了生成的代码,用我的类型替换了std_logic_vector,但这次它给了我语法错误。 你能告诉我当你处理整数类型的时候,写一个文本工作台文件的正确方法是什么吗

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.newtype.all;

ENTITY mymodule_test IS
END mymodule_test;

ARCHITECTURE behavior OF mymodule_test IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT mymodule
    PORT(
         indata : IN  row_t;
         sum : OUT  integer
        );
    END COMPONENT;


   --Inputs
   signal indata : row_t := (0,0,0);

    --Outputs
   signal sum : integer;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 

  constant <clock>_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: mymodule PORT MAP (
          indata => indata,
          sum => sum
        );

   -- Clock process definitions
   <clock>_process :process
   begin
        <clock> <= '0';
        wait for <clock>_period/2;
        <clock> <= '1';
        wait for <clock>_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  

      wait for <clock>_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;

您尚未发布遇到的语法错误。但是,如果我在Xilix ISE 14.7中创建了一个新项目,并且只添加了上述代码,则会出现以下语法错误:

错误:HDLCompiler:806- mymodule_test.vhdl
第28行:语法错误,你正在沿着正确的方向工作。测试台的自动生成器会产生垃圾,您必须修复这些垃圾。不仅是你已经完成的类型,而且你还必须像Martin Zabel所说的那样填充位。最后,此测试台将仅用于行为模拟。您很少需要后期合成或后期P&R模拟,但如果需要,您将需要一个用于门级组件的包装器,该组件只需转换端口类型。
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.newtype.all;

ENTITY mymodule_test IS
END mymodule_test;

ARCHITECTURE behavior OF mymodule_test IS 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT mymodule
    PORT(
         indata : IN  row_t;
         sum : OUT  integer
        );
    END COMPONENT;

   --Inputs
   signal indata : row_t := (0,0,0);

    --Outputs
   signal sum : integer;

BEGIN
    -- Instantiate the Unit Under Test (UUT)
   uut: mymodule PORT MAP (
          indata => indata,
          sum => sum
        );

   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  

      -- insert stimulus here 

      wait;
   end process;
END;