VHDL非解析信号&x27;i2c接收数据和x27;有多个来源
我正在通过I2C将FPGA连接到MPU-6050陀螺传感器。我已经尝试了不同的方法,但现在我得到了错误:未解决的信号‘i2c_rx_data’有多个来源(106) 你知道我做错了什么吗 格雷廷斯洛斯波斯特酒店 我的源代码:VHDL非解析信号&x27;i2c接收数据和x27;有多个来源,vhdl,fpga,Vhdl,Fpga,我正在通过I2C将FPGA连接到MPU-6050陀螺传感器。我已经尝试了不同的方法,但现在我得到了错误:未解决的信号‘i2c_rx_data’有多个来源(106) 你知道我做错了什么吗 格雷廷斯洛斯波斯特酒店 我的源代码: ----------------------------------------------------------------- -- Project : Invent a Chip -- Authors : -- Year :
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Authors :
-- Year : 2016
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- global
--reset_n : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0);
-- I2C Protokoll
i2c_sdat : inout std_logic;
i2c_sclk : inout std_logic
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- connection signals to i2c master
signal reset_n : std_logic;
signal i2c_busy : std_ulogic;
signal i2c_cs : std_ulogic;
signal i2c_mode : std_ulogic_vector(1 downto 0);
signal i2c_slave_addr : std_ulogic_vector(6 downto 0);
signal i2c_bytes_tx : unsigned(4 downto 0);
signal i2c_bytes_rx : unsigned(4 downto 0);
signal i2c_tx_data : std_ulogic_vector(7 downto 0);
signal i2c_tx_data_valid : std_ulogic;
signal i2c_rx_data : std_ulogic_vector(7 downto 0);
signal i2c_rx_data_valid : std_ulogic;
signal i2c_rx_data_en : std_ulogic;
signal i2c_error : std_ulogic;
type state_t is (S_INIT, I2C_CON, S_WAIT_TIME,I2C_READ);
signal state, state_nxt : state_t;
signal gyro : std_ulogic_vector(7 downto 0);
component i2c_master is
generic (
GV_SYS_CLOCK_RATE : natural := 50000000;
GV_I2C_CLOCK_RATE : natural := 400000; -- standard mode: (100000) 100 kHz; fast mode: 400000 Hz (400 kHz)
GW_SLAVE_ADDR : natural := 7;
GV_MAX_BYTES : natural := 16;
GB_USE_INOUT : boolean := true;
GB_TIMEOUT : boolean := false
);
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
-- i2c master
i2c_clk : inout std_logic;
-- separated in / out
i2c_clk_ctrl : out std_ulogic;
i2c_clk_in : in std_ulogic;
i2c_clk_out : out std_ulogic;
-- inout
i2c_dat : inout std_logic;
-- separated in / out
i2c_dat_ctrl : out std_ulogic;
i2c_dat_in : in std_ulogic;
i2c_dat_out : out std_ulogic;
-- interface
busy : out std_ulogic;
cs : in std_ulogic;
mode : in std_ulogic_vector(1 downto 0); -- 00: only read; 01: only write; 10: first read, second write; 11: first write, second read
slave_addr : in std_ulogic_vector(GW_SLAVE_ADDR-1 downto 0);
bytes_tx : in unsigned(to_log2(GV_MAX_BYTES+1)-1 downto 0);
bytes_rx : in unsigned(to_log2(GV_MAX_BYTES+1)-1 downto 0);
tx_data : in std_ulogic_vector(7 downto 0);
tx_data_valid : in std_ulogic;
rx_data : out std_ulogic_vector(7 downto 0);
rx_data_valid : out std_ulogic;
rx_data_en : in std_ulogic;
error : out std_ulogic
);
end component i2c_master;
begin
reset_n <= not(reset);
-- i2c master
i2c_master_inst : i2c_master
generic map (
GV_SYS_CLOCK_RATE => CV_SYS_CLOCK_RATE,
GV_I2C_CLOCK_RATE => 400000,
GW_SLAVE_ADDR => 7,
GV_MAX_BYTES => 16,
GB_USE_INOUT => true,
GB_TIMEOUT => false
)
port map (
clock => clock,
reset_n => reset_n,
i2c_clk => i2c_sclk,
i2c_clk_ctrl => open,
i2c_clk_in => '0',
i2c_clk_out => open,
i2c_dat => i2c_sdat,
i2c_dat_ctrl => open,
i2c_dat_in => '0',
i2c_dat_out => open,
busy => i2c_busy,
cs => i2c_cs,
mode => i2c_mode,
slave_addr => i2c_slave_addr,
bytes_tx => i2c_bytes_tx,
bytes_rx => i2c_bytes_rx,
tx_data => i2c_tx_data,
tx_data_valid => i2c_tx_data_valid,
rx_data => i2c_rx_data,
rx_data_valid => i2c_rx_data_valid,
rx_data_en => i2c_rx_data_en,
error => i2c_error
);
-- GPIO (0) = i2c_clk
--GPIO (1) = i2c_dat
-- 8mA on each GPIO Pins
process(clock, reset)
begin
-- asynchronous reset
if reset = '1' then
state <= S_INIT;
elsif rising_edge(clock) then
state <= state_nxt;
end if;
end process;
process(state,clock,reset)
begin
case state is
-- Initial start state
when S_INIT =>
if key(0) = '1' then
i2c_mode <= "11" ;
i2c_slave_addr <= "1101001";
i2c_sclk <= '1';
i2c_sdat <= '1';
-- next state
state_nxt <= I2C_CON;
end if;
when I2C_CON =>
i2c_sdat <= '0';
i2c_rx_data <= "1000100";
if i2c_rx_data_valid = '1' then
state_nxt <= I2C_READ;
else
state_nxt <= I2C_CON;
end if;
when I2C_READ =>
gyro <= i2c_tx_data;
when S_WAIT_TIME =>
state_nxt <= S_WAIT_TIME;
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
led_green <= (others => '0');
led_red <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl;
-----------------------------------------------------------------
--项目:发明芯片
--作者:
--年份:2016年
-----------------------------------------------------------------
图书馆ieee;
使用ieee.std_logic_1164.all;
使用ieee.numeric_std.all;
图书馆工作;
使用work.iac_pkg.all;
实体发明芯片是
港口(
--全球信号
时钟:标准逻辑;
重置:在标准逻辑中;
--全球的
--重置:在标准逻辑中;
--接口信号
--7-Seg
sevenseg__cs:输出标准逻辑;
sevenseg_wr:输出标准逻辑;
sevenseg_addr:输出标准逻辑向量(CW_addr_sevenseg-1向下至0);
sevenseg_din:标准逻辑向量(CW_数据sevenseg-1向下至0);
sevenseg dout:输出标准逻辑向量(CW数据sevenseg-1下降到0);
--模数转换器
模数转换器:输出标准逻辑;
adc_dac_wr:输出标准逻辑;
adc_dac_addr:out标准逻辑向量(CW_addr_adc_dac-1向下至0);
adc_dac_din:标准逻辑向量(CW_数据_adc_dac-1向下至0);
adc_dac_dout:输出标准逻辑向量(CW_数据_adc_dac-1向下至0);
--音频
音频:输出标准逻辑;
音频:输出标准逻辑;
音频地址:输出标准逻辑向量(CW地址音频-1向下至0);
音频din:标准逻辑矢量(CW数据音频-1向下至0);
音频输出:输出标准逻辑向量(CW数据音频-1向下至0);
左音频:标准逻辑;
音频irq右:标准逻辑;
音频确认左:输出标准逻辑;
音频确认右:输出标准逻辑;
--红外接收器
ir_cs:输出标准逻辑;
ir_wr:输出标准逻辑;
ir地址:输出标准逻辑向量(CW地址ir-1向下至0);
ir din:标准逻辑向量(CW数据ir-1向下至0);
ir dout:输出标准逻辑向量(CW数据ir-1向下至0);
ir_irq_rx:标准逻辑;
红外确认接收:输出标准逻辑;
--液晶显示器
液晶显示器:输出标准逻辑;
液晶显示器:输出标准逻辑;
lcd地址:输出标准逻辑向量(CW地址lcd-1向下至0);
lcd din:标准逻辑矢量(CW数据lcd-1向下至0);
lcd输出:输出标准逻辑向量(CW数据lcd-1向下至0);
液晶显示器:标准逻辑;
lcd确认:输出标准逻辑;
--SRAM
sram_cs:out std_ulogic;
sram_wr:out std_ulogic;
sram地址:输出标准逻辑向量(CW地址sram-1向下至0);
sram din:标准逻辑向量(CW数据sram-1向下至0);
sram dout:输出标准逻辑向量(CW数据sram-1向下至0);
--通用异步收发器
uart\u cs:out std\u ulogic;
uart\u wr:out标准逻辑;
uart地址:输出标准逻辑向量(CW地址uart-1向下至0);
uart din:标准逻辑向量(CW数据uart-1向下至0);
uart dout:输出标准逻辑向量(CW数据uart-1向下至0);
uart_irq_rx:标准逻辑;
uart\u irq\u tx:标准逻辑;
uart确认接收:输出标准逻辑;
uart确认发送:输出标准逻辑;
--GPIO
gp\u ctrl:out标准逻辑向量(15到0);
gp_in:标准逻辑向量(15到0);
gp_out:out标准逻辑向量(15到0);
--LED/开关/钥匙
绿色led:输出标准逻辑向量(8到0);
led红色:输出标准逻辑向量(17至0);
开关:标准逻辑向量(17向下至0);
键:标准逻辑向量(2到0);
--I2C原科尔
i2c_sdat:inout标准逻辑;
i2c_sclk:inout标准逻辑
);
末端发明芯片;
发明芯片rtl的体系结构是
--i2c主机的连接信号
信号复位:标准逻辑;
信号i2c_忙:标准逻辑;
信号i2c_cs:标准逻辑;
信号i2c_模式:标准逻辑向量(1到0);
信号i2c从站地址:标准逻辑向量(6到0);
信号i2c_字节_tx:无符号(4到0);
信号i2c_字节_rx:无符号(4到0);
信号i2c_tx_数据:标准逻辑向量(7到0);
信号i2c发送数据有效:标准逻辑;
信号i2c_rx_数据:标准逻辑向量(7到0);
信号i2c接收数据有效:标准逻辑;
信号i2c接收数据:标准逻辑;
信号i2c_错误:标准逻辑;
类型状态为(S_INIT、I2C_CON、S_WAIT_TIME、I2C_READ);
信号状态,状态:状态;
信号陀螺:标准逻辑矢量(7到0);
组件i2c_主机为
一般的(
GV系统时钟速率:自然:=50000000;
GV_I2C_时钟频率:自然:=400000;--标准模式:(100000)100kHz;快速模式:400000Hz(400kHz)
GW_SLAVE_ADDR:natural:=7;
GV_MAX_字节:自然:=16;
GB\U USE\U INOUT:布尔值:=真;
GB_超时:布尔值:=fals