警告（10631）：VHDL进程语句警告：推断信号或变量的锁存

我正在学习用VHDL编写代码，下面的代码在编译时没有给我错误，但给了我一个锁存警告。我需要去掉这个锁存器，因为我相信它会在下一段代码中给我带来问题，这段代码将使用这个锁存器（8x8乘法器）

指向此节点的（第33行）：

该警告会导致其他警告（对于每种类型.idle、.mid、.msb等）：

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谢谢大家!

第33行处于第二个过程中（没有标签）

为什么会有锁

参见IEEE标准1076.6-2004（撤销）RTL综合
6.2.1.1具有敏感度清单的过程的水平敏感度存储

当以下所有条件适用时，应针对信号（或变量）对电平敏感存储元件进行建模：

a） 信号（或变量）具有显式赋值。
b） 信号（或变量）没有作为条件的执行路径。
c） 有些进程的执行不执行对信号（或变量）的显式赋值（通过赋值语句）

默认情况下，信号（或变量）的标识赋值的效果应与不存在赋值的情况相同。 如果组合属性修饰信号（或变量），则应合成带反馈的组合逻辑

为避免意外锁定，条件c）必须无效

问题代码中可能导致锁存的示例：

当msb=>
如果start='0'，则
如果（count=“11”），则
下一步，说明撤销的IEEE Std 1076.6 RTL综合标准解释了如何推断锁存-6.2.1.1根据灵敏度列表中的过程进行电平敏感存储“当以下所有条件均适用时，应对信号（或变量）的电平敏感存储元件进行建模：A）信号（或变量）具有明确的分配。b）信号（或变量）没有作为条件的执行路径。c）有一些进程的执行没有执行（通过赋值语句）到信号（或变量）的显式赋值。“也就是说，推断锁存的风险主要出现在多个条件导致锁存启用时。布线、扇出和上升和下降时间的差异可能会产生使能故障。顺序状态机实现的乘法器不太可能通过启用的锁存器受到额外的传播延迟的影响。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY control IS
    PORT (
        clk, reset_a, start : IN STD_LOGIC;
        count : IN UNSIGNED (1 DOWNTO 0);
        input_sel, shift_sel : OUT UNSIGNED(1 DOWNTO 0);
        state_out : OUT UNSIGNED(2 DOWNTO 0);
        done, clk_ena, sclr_n : OUT STD_LOGIC
        );

END ENTITY control;

ARCHITECTURE logic OF control IS

    type logic_state is (idle, lsb, mid, msb, calc_done, err);

    signal current_state: logic_state;
    signal next_state: logic_state;

BEGIN
    PROCESS (clk, reset_a)
    BEGIN
        if reset_a = '1' then
            current_state <= idle;
        elsif rising_edge (clk) then
            current_state <= next_state;
        end if;
    END PROCESS;

    PROCESS (current_state, start, count)
    BEGIN

    CASE current_state IS
        when idle =>
        if start = '1' then
            next_state <= lsb;
        else
            next_state <= idle;
        end if;

        when lsb =>
        if start = '0' and count = "00" then
            next_state <= mid;
        else
            next_state <= err;
        end if;

        when mid =>
        if start = '0' then
            if (count = "01") then
                next_state <= mid;
            elsif (count = "10") then
                next_state <= msb;
            else
                next_state <= err;
            end if;
        end if;

        when msb =>
        if start = '0' then
            if (count = "11") then
                next_state <= calc_done;
            else
                next_state <= err;
            end if;
        end if;

        when calc_done =>
        if start = '0' then
            next_state <= idle;
        else
            next_state <= err;
        end if;

        when err =>
        if start = '1' then
            next_state <= lsb;
        else
            next_state <= err;
        end if;

    END CASE;
    END PROCESS;

    mealy: PROCESS (current_state, start, count) 
    BEGIN     
        input_sel <= "00";
        shift_sel <= "00";
        done <= '0';
        clk_ena <= '0';
        sclr_n <= '1';

    CASE current_state IS
        when idle =>
        if start = '1' then
            sclr_n <= '0';
            clk_ena <= '1';
        END IF;

        when lsb =>
        if start = '0' and count = "00" then
            sclr_n <= '1';                                                                       
        end if;

        when mid =>
        if start = '0' then
            if (count = "01") then
                input_sel <= "01";
                shift_sel <= "01";
            elsif (count = "10") then
                input_sel <= "10";
                shift_sel <= "01";
            end if;
        end if;

        when msb =>
        if start = '0' then
            if (count = "11") then
                input_sel <= "11";
                shift_sel <= "10";
            end if;
        end if;

        when calc_done =>
        if start = '0' then
            input_sel <= "00";
            shift_sel <= "00";
            done <= '1';
            clk_ena <= '0';
        end if;

        when err =>
        if start = '1' then
            input_sel <= "00";
            shift_sel <= "00";
            done <= '0';
            clk_ena <= '1';
            sclr_n <= '0';
        end if;

    END CASE;
    END PROCESS mealy;

    moore: PROCESS(current_state)
    BEGIN
        state_out <= "000";

    CASE current_state IS
        WHEN idle =>

        WHEN lsb =>
            state_out <= "001";

        WHEN mid =>
            state_out <= "010";

        WHEN msb =>
            state_out <= "011";

        WHEN calc_done =>
            state_out <= "100";

        WHEN err =>
            state_out <= "101";

    END CASE;
    END PROCESS moore;
END ARCHITECTURE logic;

Warning (10631): VHDL Process Statement warning at mult_control.vhd(65): inferring latch(es) for signal
or variable "next_state", which holds its previous value in one or more paths through the process

    PROCESS (current_state, start, count)

Warning (13012): Latch next_state.idle_218 has unsafe behavior
    Warning (13013): Ports D and ENA on the latch are fed by the same signal start