带有select when错误的VHDL

带有select when错误的VHDL,vhdl,Vhdl,VHDL是我所见过的设计最差、语法最差的语言。 当代码给我一个错误时,为什么这与select有关 library ieee; use ieee.std_logic_1164.all; entity mux48 is port( mux48dv0:in std_logic_vector(7 downto 0); mux48dv1:in std_logic_vector(7 downto 0); mux48dv2:in std_logic_vector(7 downto 0)

VHDL是我所见过的设计最差、语法最差的语言。 当代码给我一个错误时,为什么这与select有关

  library ieee;
use ieee.std_logic_1164.all;

entity mux48 is
port(
   mux48dv0:in std_logic_vector(7 downto 0);
   mux48dv1:in std_logic_vector(7 downto 0);
   mux48dv2:in std_logic_vector(7 downto 0);
   mux48dv3:in std_logic_vector(7 downto 0);
   mux48sv:in std_logic_vector(3 downto 0);
   mux48ov:out std_logic_vector(7 downto 0)
);
end mux48;

architectre mux48_df of mux48 is
begin
    with mux48sv select
    mux48ov <= mux48dv0 when "0000",
        <= mux48dv1 when "0001",
        <= mux48dv2 when "0010",
        <= mux48dv3 when "0011",
        <= mux48dv0 when "0100",
        <= mux48dv1 when "0101",
        <= mux48dv2 when "0110",
        <= mux48dv3 when "0111",
        <= mux48dv0 when "1000",
        <= mux48dv1 when "1001",
        <= mux48dv2 when "1010",
        <= mux48dv3 when "1011",
        <= mux48dv0 when "1100",
        <= mux48dv1 when "1101",
        <= mux48dv2 when "1110",
        <= mux48dv3 when "1111";
end mux48_df;

您有几个语法错误:赋值应该如下所示

with mux48sv select
   mux48ov <= mux48dv0 when "0000",
              mux48dv1 when "0001",
              ...
              mux48dv3 when others;
使用mux48sv选择

mux48ov VHDL有很多问题和怪癖,但如果正确使用,它是该领域最好的语言。你不会通过严厉地、先发制人地批评一种你刚刚学会的语言来鼓励对你的问题做出好的回答。那么哪种语言容忍关键字中的拼写错误呢?指定一个16:1的mux并称之为Mux4似乎有些奇怪。如果您正在进行字节车道转向,并且重新排序是常规的,您可以创建一个select(1向下到0)信号并将其分配给它,
mux48sel它不是一个16:1的mux;这是一个4:1的多路复用器,有12行无用的额外代码,因为他选择与VHDL抗争而不是使用它。
with mux48sv select
   mux48ov <= mux48dv0 when "0000",
              mux48dv1 when "0001",
              ...
              mux48dv3 when others;