UART在VHDL中接收数据

我正在尝试用VHDL代码构建一个简单的UART，它接收一个字符，然后发送回PC。 我的程序基于此示例代码。UART传输工作正常，但在UART接收的情况下，它没有收到任何信息。 合成完成后，出现了一些关于ff/latch的警告，使“存储”数据为常量值

WARNING:Xst:1293 - FF/Latch <store_2> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <store_3> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <store_4> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <store_5> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <store_6> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <store_7> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <state1_FSM_FFd8> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <state1_FSM_FFd5> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <state1_FSM_FFd7> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <state1_FSM_FFd6> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <state1_FSM_FFd4> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <state1_FSM_FFd3> has a constant value of 0 in block <uart>. This FF/Latch will be trimmed during the optimization process.

警告：Xst:1293-FF/Latch在块中的常量值为0。此FF/闩锁将在优化过程中进行修剪。
警告：Xst:1896-由于其他FF/Latch微调，FF/Latch在块中的常量值为0。此FF/闩锁将在优化过程中进行修剪。
警告：Xst:1896-由于其他FF/Latch微调，FF/Latch在块中的常量值为0。此FF/闩锁将在优化过程中进行修剪。
警告：Xst:1896-由于其他FF/Latch微调，FF/Latch在块中的常量值为0。此FF/闩锁将在优化过程中进行修剪。
警告：Xst:1896-由于其他FF/Latch微调，FF/Latch在块中的常量值为0。此FF/闩锁将在优化过程中进行修剪。
警告：Xst:1896-由于其他FF/Latch微调，FF/Latch在块中的常量值为0。此FF/闩锁将在优化过程中进行修剪。
警告：Xst:1896-由于其他FF/Latch微调，FF/Latch在块中的常量值为0。此FF/闩锁将在优化过程中进行修剪。
警告：Xst:1896-由于其他FF/Latch微调，FF/Latch在块中的常量值为0。此FF/闩锁将在优化过程中进行修剪。
警告：Xst:1896-由于其他FF/Latch微调，FF/Latch在块中的常量值为0。此FF/闩锁将在优化过程中进行修剪。
警告：Xst:1896-由于其他FF/Latch微调，FF/Latch在块中的常量值为0。此FF/闩锁将在优化过程中进行修剪。
警告：Xst:1896-由于其他FF/Latch微调，FF/Latch在块中的常量值为0。此FF/闩锁将在优化过程中进行修剪。
警告：Xst:1896-由于其他FF/Latch微调，FF/Latch在块中的常量值为0。此FF/闩锁将在优化过程中进行修剪。

请帮助我并提前感谢！这是我的基本代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity uart is
port (   clk   : in   std_logic;
         rx    : in   std_logic;
         tx    : out  std_logic);

end uart;

architecture Behavioral of uart is
--fsm for transmission
type fsm  is (idle,b1,b2,b3,b4,b5,b6,b7,b8,b9);                         
signal state  : fsm  := idle;

--fsm for reception
type fsm1 is (idle1,b11,b21,b31,b41,b51,b61,b71,b81,b91);       
signal state1 : fsm1 := idle1;

signal start  : std_logic;
signal store  : std_logic_vector (7 downto 0) := "00000000"; 
--store received data

begin

--reception
process(clk)
variable i : integer := 0;  --baudtick
begin
if clk'event and clk = '1' then 
    i := i + 1;

    if state1 = idle1 then
    start <= rx;
    end if;
    if start = '0' then  --check start bit 0
    state1 <= b11;
    elsif start = '1' then
    state1 <= idle1;
    end if;

    --store 8 bits
    if (state1 = b11) then --1
    store(0) <= rx;
        if i = 26042 then
        state1 <= b21;
        i := 0;
        end if;
    end if;

    if (state1 = b21) then --2
    store(1) <= rx;
        if i = 26042 then
        state1 <= b31;
        i := 0;
        end if;
    end if;

    if (state1 = b31) then --3
    store(2) <= rx;
        if i = 26042 then
        state1 <= b41;
        i := 0;
        end if;
    end if;

    if (state1 = b41) then --4
    store(3) <= rx;
        if i = 26042 then
        state1 <= b51;
        i := 0;
        end if;
    end if;

    if (state1 = b51) then --5
    store(4) <= rx;
        if i = 26042 then
        state1 <= b61;
        i := 0;
        end if;
    end if;

    if (state1 = b61) then --6
    store(5) <= rx;
        if i = 26042 then
        state1 <= b71;
        i := 0;
        end if;
    end if;

    if (state1 = b71) then --7
    store(6) <= rx;
        if i = 26042 then
        state1 <= b81;
        i := 0;
        end if;
    end if;

    if (state1 = b81) then --8
    store(7) <= rx;
        if i = 26042 then
        state1 <= idle1;
        i := 0;
        end if;
    end if;     
  end if;
end process;

--transmission      
process(clk)
variable i : integer := 0;  --baudtick
begin
if clk'event and clk = '1' then 
    i := i + 1;

    if state = idle then
        if start = '0' then  --send start bit 0
        tx <= '0';
            if i = 26042 then
            state <= b1;
            i := 0;
            end if;
        elsif start = '1' then
        state <= idle;
        end if;
    end if;

    --send 8 bits
    if (state = b1) then --1
    tx <= store(0);
        if i = 26042 then
        state <= b2;
        i := 0;
        end if;
    end if;

    if (state = b2) then --2
    tx <= store(1);
        if i = 26042 then
        state <= b3;
        i := 0;
        end if;
    end if;

    if (state = b3) then --3
    tx <= store(2);
        if i = 26042 then
        state <= b4;
        i := 0;
        end if;
    end if;

    if (state = b4) then --4
    tx <= store(3);
        if i = 26042 then
        state <= b5;
        i := 0;
        end if;
    end if;

    if (state = b5) then --5
    tx <= store(4);
        if i = 26042 then
        state <= b6;
        i := 0;
        end if;
    end if;

    if (state = b6) then --6
    tx <= store(5);
        if i = 26042 then
        state <= b7;
        i := 0;
        end if;
    end if;

    if (state = b7) then --7
    tx <= store(6);
        if i = 26042 then
        state <= b8;
        i := 0;
        end if;
    end if;

    if (state = b8) then --8
    tx <= store(7);
        if i = 26042 then
        state <= b9;
        i := 0;
        end if;
    end if;

    if (state = b9) then --stop
    tx <= '1';
        if i = 26042 then
        state <= idle;
        i:= 0;
        end if;
    end if;
 end if;
 end  process;
 end Behavioral;

IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
使用IEEE.STD_LOGIC_ARITH.ALL；
使用IEEE.STD_LOGIC_UNSIGNED.ALL；
实体uart是
端口（时钟：在标准逻辑中；
rx：标准逻辑中；
tx：输出标准（U逻辑）；
结束uart；
uart的体系结构是
--传输用fsm
fsm类型为（怠速、b1、b2、b3、b4、b5、b6、b7、b8、b9）；
信号状态：fsm:=空闲；
--用于接收的fsm
fsm1型为（idle1、b11、b21、b31、b41、b51、b61、b71、b81、b91）；
信号状态1:fsm1:=idle1；
信号启动：标准逻辑；
信号存储：标准逻辑向量（7到0）：=“00000000”；
--存储接收到的数据
开始
--接待
过程（clk）
变量i：整数：=0--鲍迪克
开始
如果clk'事件和clk='1'，则
i:=i+1；
如果state1=idle1，则
开始关于“FF/闩锁修剪”的警告表示合成工具已确定设计的某些部分（在本例中为FFs）未使用，因此可以删除。对于特定代码，它表示设计中存在缺陷，因为要使设计正常工作，所有8位
存储都是必需的

在进行综合设计时，您应该先模拟代码以确保功能正确，然后再尝试在硬件（FPGA）上进行设计。对您的设计进行这样的模拟将揭示出它没有按预期工作的原因。ModelSim模拟器在英特尔Quartus套件中免费提供，用于小型设计

您可能应该查看接收过程中的第一行：

...
if state1 = idle1 then
    start <= rx;
end if;
if start = '0' then  --check start bit 0
    state1 <= b11;
...

。。。
如果state1=idle1，则
开始1/您的接收似乎直接来自外部。你必须先同步。2/波特率相当“静态”。3/尝试开始使用循环来处理8位。如果您有一个协议要求您接收/发送328位，该怎么办？