后进先出存储器vhdl代码理解

我有一个后进先出存储器的代码，我不明白为什么在27行上（如果（last=n-2），那么full最后一个

在
范围-1到n-1
，当
最后一个
为n-1时，它表示完全后进先出，并且
full
必须很高（
'1'
）

当接受写入时，
last
随
last递增1
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lifo is
  generic(n : natural := 4);
  port(Din         : in  std_logic_vector(3 downto 0);
       Dout        : out std_logic_vector(3 downto 0);
       wr          : in  std_logic;
       rd          : in  std_logic;
       empty, full : out std_logic;
       clk         : in  std_logic);
end entity lifo;

architecture arh of lifo is
  type memorie is array(0 to n-1) of std_logic_vector(3 downto 0);
  signal mem  : memorie := (others => (others => '0'));
  signal last : integer range -1 to n-1;
begin
  process(clk)
  begin
    if (rising_edge(clk)) and (wr = '1') then
      if (last = n-1) then null;
      else
        if(last = n-2) then full <= '1'; end if;
        if(last = -1) then empty <= '0'; end if;
        mem(last + 1)            <= Din;
        last                     <= last + 1;
      end if;
    elsif (rising_edge(clk)) and (rd = '1') then
      if(last = -1) then null;
      else
        Dout                     <= mem(last);
        last                     <= last - 1; full <= '0';
        if(last = -1) then empty <= '1'; end if;
      end if;
    end if;
  end process;
end architecture arh;