Vhdl Can';t推断寄存器,因为其行为不';不匹配Quartus II中的任何受支持模型
守则:Vhdl Can';t推断寄存器,因为其行为不';不匹配Quartus II中的任何受支持模型,vhdl,quartus,Vhdl,Quartus,守则: library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity decoder10 is port( in_data: in STD_LOGIC_VECTOR (7 downto 0); clk : in
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity decoder10 is
port( in_data: in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
out_data: out STD_LOGIC_VECTOR (7 downto 0));
end decoder10;
architecture behavioral of decoder10 is
signal int_bus1 : STD_LOGIC_VECTOR (63 downto 0);
signal int_bus2 : STD_LOGIC_VECTOR (63 downto 0);
signal int_bus3 : STD_LOGIC_VECTOR (31 downto 0);
signal lower : STD_LOGIC_VECTOR (31 downto 0);
signal higher : STD_LOGIC_VECTOR (31 downto 0);
signal intermid : STD_LOGIC_VECTOR (31 downto 0);
signal curr_key : STD_LOGIC_VECTOR (31 downto 0);
signal got_data: std_logic; --data written in
signal variable_test: std_logic:= '0';
signal n_ready: std_logic; --code assembled
signal k_ready: std_logic; --key selected
signal k_added: std_logic; --key added
signal sub_ready: std_logic; --blocks substituted
signal sh_ready: std_logic; --shift done
signal xor_ready: std_logic; --xor done
signal out_ready: std_logic; --ready for output
signal sent_data: std_logic; --data written out
signal start_again: std_logic; --start the main step again
type arr is array (0 to 15) of std_logic_vector(31 downto 0);
type key is array (0 to 7) of std_logic_vector(31 downto 0);
type key_num is array (0 to 31) of integer;
signal key_it : key_num := (0,1,2,3,4,5,6,7,
7,6,5,4,3,2,1,0,
7,6,5,4,3,2,1,0,
7,6,5,4,3,2,1,0);
signal tab : arr := (X"00000001",
X"00000002",
X"00000003",
X"00000004",
X"00000005",
X"00000006",
X"00000007",
X"00000008",
X"00000009",
X"0000000a",
X"0000000b",
X"0000000c",
X"0000000d",
X"0000000e",
X"0000000f",
X"00000000");
signal tab_key : key := (X"00000007",
X"00000006",
X"00000005",
X"00000004",
X"00000003",
X"00000002",
X"00000001",
X"00000000");
component adder is
port( dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
END component;
begin
add1: adder
port map (lower, curr_key, int_bus3);
process (clk, in_data)
variable i: INTEGER := 0;
variable j: INTEGER := 0;
variable k: INTEGER := 0;
begin
-- assembling input code into one piece
if (rising_edge(clk)) then
if (i<8) then
int_bus1(63 downto 56)<=in_data;
got_data <= '1';
n_ready <= '0';
if (got_data = '1') then
--shift right 8 bits
int_bus1(55 downto 0) <= int_bus1(63 downto 8);
i := i + 1;
got_data <= '0';
end if;
end if;
if (i = 8 and n_ready = '0' and out_ready = '0') then
lower<=int_bus1(31 downto 0);
higher<=int_bus1(63 downto 32);
n_ready <= '1';
start_again <= '1';
end if;
end if;
if (n_ready ='1') then
-- base encryption step
if (rising_edge(clk)) then
if (j <32 and start_again = '1') then
-- key/step dependence
curr_key <= tab_key(key_it(j));
k_ready <= '1';
start_again <= '0';
end if;
if (k_ready = '1') then
lower <= curr_key + lower;
k_added <= '1';
k_ready <='0';
end if;
if (k_added = '1') then
--block substitution
lower(3 downto 0) <= tab(CONV_INTEGER(lower(3 downto 0)))(3 downto 0);
lower(7 downto 4) <= tab(CONV_INTEGER(lower(7 downto 4)))(7 downto 4);
lower(11 downto 8) <= tab(CONV_INTEGER(lower(11 downto 8)))(11 downto 8);
lower(15 downto 12) <= tab(CONV_INTEGER(lower(15 downto 12)))(15 downto 12);
lower(19 downto 16) <= tab(CONV_INTEGER(lower(19 downto 16)))(19 downto 16);
lower(23 downto 20) <= tab(CONV_INTEGER(lower(23 downto 20)))(23 downto 20);
lower(27 downto 24) <= tab(CONV_INTEGER(lower(27 downto 24)))(27 downto 24);
lower(31 downto 28) <= tab(CONV_INTEGER(lower(31 downto 28)))(31 downto 28);
sub_ready <= '1';
k_added <= '0';
end if;
if (sub_ready = '1') then
--shift 11 bits right cyclically
lower(31 downto 21) <= lower(10 downto 0);
lower(20 downto 0) <= lower(31 downto 11);
sh_ready<= '1';
sub_ready <= '0';
end if;
if (sh_ready = '1') then
higher <= lower xor higher;
lower <= higher;
sh_ready<= '0';
j:=j+1;
start_again <= '1';
out_ready <= '0';
end if;
end if;
end if;
if (rising_edge(clk)) then
if (j = 32 and out_ready = '0') then
j:=j+1;
variable_test <= '1'; --artifact of testing the behavior of variables
end if;
end if;
-- assembling output code into one piece
if (rising_edge(clk)) then
if (out_ready = '0' and variable_test = '1') then
int_bus2 (63 downto 32) <= higher;
int_bus2 (31 downto 0) <= lower;
out_ready <= '1';
n_ready <= '0';
end if;
if (out_ready = '1' and k<8) then
out_data<=int_bus2(7 downto 0);
sent_data <= '1';
if (sent_data ='1') then
--shift right 8 bits
int_bus2(55 downto 0) <= int_bus2(63 downto 8);
k := k + 1;
sent_data <= '0';
end if;
end if;
end if;
end process;
end behavioral;
IEEE库;
使用IEEE.std_logic_1164.all;
使用ieee.numeric_std.all;
使用ieee.std_logic_unsigned.all;
实体解码器10是
端口(in_数据:in STD_逻辑_向量(7到0);
clk:标准逻辑中;
out_数据:out STD_逻辑_向量(7到0));
末端解码器10;
解码器10的体系结构是
信号int_总线1:STD_逻辑_向量(63向下至0);
信号int_总线2:标准逻辑向量(63至0);
信号int_总线3:标准逻辑向量(31至0);
信号降低:标准逻辑向量(31向下至0);
信号较高:标准逻辑向量(31至0);
信号间歇:标准逻辑向量(31至0);
信号电流键:标准逻辑向量(31至0);
信号获取_数据:标准_逻辑--写入的数据
信号变量_测试:标准_逻辑:='0';
信号n_就绪:标准_逻辑--代码汇编
信号k_就绪:标准_逻辑--选择的键
添加信号k_:标准_逻辑--加键
信号子单元就绪:标准单元逻辑--替换块
信号sh_就绪:标准_逻辑--交接班
信号异或就绪:标准逻辑--异或完成
信号输出准备就绪:标准逻辑--准备输出
信号发送数据:标准逻辑--写出的数据
信号再次启动:标准逻辑--重新开始主要步骤
arr型是标准逻辑向量(31到0)的数组(0到15);
类型键是标准逻辑向量(31到0)的数组(0到7);
类型key_num是整数的数组(0到31);
信号键:键号:=(0,1,2,3,4,5,6,7,
7,6,5,4,3,2,1,0,
7,6,5,4,3,2,1,0,
7,6,5,4,3,2,1,0);
信号选项卡:arr:=(X“00000001”,
X“00000002”,
X“00000003”,
X“00000004”,
X“00000005”,
X“00000006”,
X“00000007”,
X“00000008”,
X“00000009”,
X“0000000 A”,
X“0000000b”,
X“0000000c”,
X“0000000d”,
X“0000000 E”,
X“0000000 f”,
X“00000000”);
信号选项卡_键:键:=(X“0000000 7”,
X“00000006”,
X“00000005”,
X“00000004”,
X“00000003”,
X“00000002”,
X“00000001”,
X“00000000”);
元件加法器
端口(数据A:标准逻辑向量(31到0);
数据:标准逻辑向量(31到0);
结果:输出标准逻辑向量(31到0);
端部元件;
开始
地址1:加法器
端口图(下部、电流键、int_总线3);
过程(时钟、输入数据)
变量i:整数:=0;
变量j:整数:=0;
变量k:整数:=0;
开始
--将输入代码组装成一个整体
如果(上升沿(clk)),则
如果(i这很可能是因为您的时钟启用比您的时钟具有更高的优先级,并且不存在允许这样做的FPGA硬件。每当您编写合成代码时,您需要考虑这是否可以实际映射到底层硬件。
所以不是
if (n_ready ='1') then
-- base encryption step
if (rising_edge(clk)) then
(...)
尝试:
请看一看——它是为Xilinx FPGA编写的,但我猜类似的东西也适用于其他产品。第一个答案,由sonicwave给出,并不是严格地适用于所有体系结构,尽管我认为在这种情况下是正确的。
一个if后跟一个edge可以由一个门控时钟实现,但这样做并不是一个好主意在所有类型的FPGA或CPLD架构中都支持r
一些提示:
将tab和tab_键更改为常量。它们从未分配,因此不需要信号。将它们设置为信号可能意味着它们在某些架构中是统一的
整个过程应该使用进程,而不是使用顺序逻辑。这会导致“推断锁存”错误,因为取决于通过代码的路径,重新启动可能会被写入,也可能不会被写入。为避免推断锁存,请确保通过所有路径写入信号或在进程内计时
您需要记住,VHDL不是一种编程语言,它是一种描述语言。除非系统是同步的,否则所有行都是同时执行的。例如,在第147行,您有两行同时操作较高和较低的代码
如果你告诉我你想要实现什么,我可以为你重写
if(rising_edge(clk)) then
if(n_ready = '1') then
(...)