Vhdl 解析字符串数组

我想在VHDL字符串数组中解析单独的字符。 实际代码相当大，99.99%的代码与此问题无关

我得到一个错误：错误：索引名称不是“std\U逻辑\U向量”

示例代码：

  component TestRun is
   port ( StrAr : in string(1 to 3) :="ABC" );
   ...
   signal Char_Two : std_logic_vector( 7 downto 0 );

正确的语法是什么：

Char_Two <= StrAr(1); -- ie Char_Two = 'B'

---

Char\u Two这是语义而不是语法，std\u逻辑\u向量与类型字符无关。另外一个字符（1）是字符“A”。要将字符枚举的二进制位置值指定给std_逻辑_向量，需要能够将整数类型转换为二进制表示。这句话的意思是：谢谢你的回答，成功了！你真的帮了我大忙。
entity TestRun is
 Port ( led0  : out std_logic := '0';
        led1  : out std_logic := '0';
        led2  : out std_logic := '0'
 );
end TestRun;

architecture rtl of TestRun is

signal StrAr : string(1 to 3):= "ABC";
signal Char_Two : std_logic_vector( 7 downto 0);
signal AA : std_logic_vector( 7 downto 0) := "01000001";
signal BB : std_logic_vector( 7 downto 0) := "01000010";
signal CC : std_logic_vector( 7 downto 0) := "01000011";

begin

Char_Two <= std_logic_vector(to_unsigned(character'pos(StrAr(1)), Char_Two'length));

  test1: process (Char_Two, AA, BB, CC)
     begin

     if (Char_Two = AA) then
       led0 <= '1';
     elsif ( Char_Two = BB)then
        led1 <= '1';
     elsif ( Char_Two = CC)then 
        led2 <= '1';
     else 
        led0 <= '0';
        led1 <= '0';
        led2 <= '0';
     end if;

   end process;
end rtl;