用vhdl解决vivado约束问题

我对vivado的用法不太熟悉。我对FSM的合成后计时模拟有问题。模拟无法在多方面工作（行为模拟和合成后功能模拟工作）。 约束可能存在一些问题（我使用约束向导创建约束）。 时钟频率=200赫兹

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity control_asy_gate is
  Port ( clk : in STD_LOGIC;
     rst_in : in STD_LOGIC;
     full : in STD_LOGIC;
     fine : in STD_LOGIC;
     empty : in STD_LOGIC;
     busy : in STD_LOGIC;
     rst_out : out STD_LOGIC;
     data_valid : out STD_LOGIC;
     en_rom : out STD_LOGIC;
     en_comp : out STD_LOGIC;
     en_divisore : out STD_LOGIC;
     en_trasm : out STD_LOGIC);
 end control_asy_gate;

architecture Behavioral of control_asy_gate is

TYPE stati IS (init,trasmetti,compara,acquisizione,reset);
SIGNAL state: stati;
SIGNAL counter_rst: integer range 0 to 2:=0;


begin
en_divisore<= not fine;
comb: PROCESS (clk,rst_in, full, empty,state,busy)
begin

 if rst_in='1' then
    state<=init; 
   counter_rst<=0;   
 else

 CASE state IS 
    WHEN init=>
          if rising_edge(clk) then
              state<= reset;
          end if;     
    WHEN reset=>
      if rising_edge(clk) then
         if counter_rst=2 then
             state<= trasmetti;
             counter_rst<=0;                      
         else
            counter_rst<=counter_rst+1;
            state<= reset;
         end if;
       end if;
    WHEN trasmetti=>
        if full='1' then
          state<= compara;
        else
          state<= trasmetti;               
        end if;

    WHEN compara=> 
       if empty='1' then                                  
          state<= acquisizione; 
      else             
          state<= compara;      
      end if;  
    WHEN acquisizione=>
         if busy='1' then
                state<=trasmetti;                 
         else
             state<=acquisizione;       
         end if;            
  end CASE;
end if; 
end process;

PROCESS (state)
begin

 CASE state IS 
   WHEN init=> 
     en_rom<='0';
     rst_out<='0';      
     en_trasm<='0';
     en_comp<='0'; 
     data_valid<='0';

   WHEN reset=>
      rst_out<='1';
      en_trasm<='0';
      en_comp<='0';
      en_rom<='0';
      data_valid<='0';

   WHEN trasmetti=> 
       en_rom<='1';
       rst_out<='0';      
       en_trasm<='1';
       en_comp<='0';
       data_valid<='0'; 

   WHEN compara=>
      en_rom<='1';
      rst_out<='0'; 
      en_trasm<='0';
      en_comp<='1';
      data_valid<='0';

    WHEN acquisizione=> 
          en_rom<='0';
          rst_out<='0';      
          en_trasm<='0';
          en_comp<='0';
          data_valid<='1';  
  end CASE;
end process;
end Behavioral;

---

你能帮我理解我错在哪里以及如何解决这个问题吗？

ahmedus是对的：你的代码不是寄存器传输级别（RTL）。它的合成方式将不同于你所期望的。约束向导确定了许多应该是常规逻辑信号的时钟。这表明您的代码与您想要设计的内容不符。将同步过程（仅灵敏度列表中的时钟和复位）和组合过程分开。

过程

comb

混淆了顺序逻辑和组合逻辑。首先，您应该检查RTL，而不是约束。请在谷歌上搜索VHDL中正确的同步进程语法。网上有很多例子。例如，您缺少

上升沿（clk）

。还可以查看FPGA/ASIC工具制造商关于VHDL合成指南的文档

 create_clock -period 5000000000.000 -name clk -waveform {0.0002500000000.000} [get_ports clk]
create_generated_clock -name {state_reg[0]__0_LDC_n_0} -source [get_pins{state_reg[0]__0_LDC/G}] -divide_by 1 [get_pins {state_reg[0]__0_LDC/Q}]
 create_generated_clock -name {state_reg[0]__0_P_n_0} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[0]__0_P/Q}]
 create_generated_clock -name {state_reg[1]__0_P_n_0} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[1]__0_P/Q}]
 create_generated_clock -name {state_reg[2]__0_C_n_0} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[2]__0_C/Q}]
 create_generated_clock -name {state_reg__0[0]} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[0]/Q}]
 create_generated_clock -name {state_reg__0[2]} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[2]/Q}]
 set_input_delay -clock [get_clocks clk] -min -add_delay 1.210 [get_ports busy]
 set_input_delay -clock [get_clocks clk] -max -add_delay 2.250 [get_ports busy]
set_input_delay -clock [get_clocks clk] -clock_fall -min -add_delay 1.210 [get_ports empty]
set_input_delay -clock [get_clocks clk] -clock_fall -max -add_delay 2.250 [get_ports empty]
set_input_delay -clock [get_clocks clk] -min -add_delay 1.210 [get_ports empty]
 set_input_delay -clock [get_clocks clk] -max -add_delay 2.250 [get_ports empty]
set_input_delay -clock [get_clocks clk] -clock_fall -min -add_delay 1.210 [get_ports full]
 set_input_delay -clock [get_clocks clk] -clock_fall -max -add_delay 2.250 [get_ports full]
set_input_delay -clock [get_clocks clk] -min -add_delay 1.210 [get_ports full]
set_input_delay -clock [get_clocks clk] -max -add_delay 2.250 [get_ports full]
set_input_delay -clock [get_clocks clk] -clock_fall -min -add_delay 1.210 [get_ports rst_in]
set_input_delay -clock [get_clocks clk] -clock_fall -max -add_delay 4.250 [get_ports rst_in]
set_input_delay -clock [get_clocks clk] -min -add_delay 1.210 [get_ports rst_in]
set_input_delay -clock [get_clocks clk] -max -add_delay 4.250 [get_ports rst_in]
create_clock -period 100.000 -name virtual_clock
set_input_delay -clock [get_clocks virtual_clock] -min -add_delay 1.000 [get_ports fine]
set_input_delay -clock [get_clocks virtual_clock] -max -add_delay 6.000 [get_ports fine]
set_output_delay -clock [get_clocks virtual_clock] -min -add_delay 8.000 [get_ports en_divisore]
set_output_delay -clock [get_clocks virtual_clock] -max -add_delay 15.000 [get_ports en_divisore]