Vhdl 如何修复代码中的“索引名称不是标准逻辑向量”错误

我试图通过简单地计算普通代码，然后将其转换为格雷码来制作一个格雷码计数器

我得到这个错误

Line 52: Indexed name is not a std_logic_vector

即使我声明该信号为std_逻辑_向量

GrayCount <= count(3) & count(3) xor count(2) & count(2) xor count (1) & count (1) xor count(0);

这是52。线

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity GrayCounter is
     Port ( clock : in  STD_LOGIC;
              ud : in  STD_LOGIC;
              freq_sel : in  STD_LOGIC_VECTOR (1 downto 0);
              GrayCount : out  std_logic_vector (3 downto 0));
end GrayCounter;

architecture Behavioral of GrayCounter is
    signal count : std_logic_vector(3 downto 0);
    signal hz : integer range 0 to 100000000;
    signal clk  : std_logic;
begin
    process(clock)
    begin 
        case freq_sel is
            when "00" => hz <= 2000000;  
            when "01" => hz <= 4000000;
            when "10" => hz <= 10000000;
            when others => hz <= 100000000;
        end case;
    end process;

    process(clock)
    variable temp : integer range 0 to 100000000;
    begin
        if(clock'event and clock = '1') then
            temp := temp + 1;
            if (temp>(hz/2)) then 
                clk <= not clk;
                temp := 0;
            end if;
        end if;
    end process;

    process(clk)
    begin
        if(clk'event and clk = '1') then
            if(ud = '1') then
                count <= count + 1;
            else
                count <= count - 1 ;
            end if;
        end if;
    end process;

    GrayCount <= count(3) & count(3) xor count(2) & count(2) xor count (1) & count (1) xor count(0);

end Behavioral;

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运算符优先级可能不是您所期望的

您应该添加括号：

GrayCount  <= count(3) & (count(3) xor count(2)) & (count(2) xor count (1)) & (count (1) xor count(0));

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运算符优先级可在IEEE Std 1076-2008 9.2运算符中找到，其中添加运算符9.2.5和的优先级高于逻辑运算符9.2.2，xor。串联提供一维数组的值，其长度由其操作数决定。原始操作数在长度为2的左操作数和std_logic_向量基类型std_ulogic的单个元素之间有一个最终的异或。这会导致错误。