32位比较器波形问题(VHDL)
我的波形没有改变: 我正在做我的32位比较器项目。我已经有一个1位了。我不知道问题在哪里。有人能帮我找到吗 非常感谢 代码: 1比特:32位比较器波形问题(VHDL),vhdl,Vhdl,我的波形没有改变: 我正在做我的32位比较器项目。我已经有一个1位了。我不知道问题在哪里。有人能帮我找到吗 非常感谢 代码: 1比特: IEEE库; 使用IEEE.STD_LOGIC_1164.ALL; 实体comp1是 端口(a:标准_逻辑中; b:标准逻辑; g:标准逻辑; l:在标准逻辑中; e:标准逻辑; 伟大:走出标准逻辑; 减:输出标准逻辑; 相等:输出标准(U逻辑); 结束; comp1的架构comp1是 信号s1、s2、s3:标准_逻辑; 开始 s1 b_32, g_32=>g
IEEE库;
使用IEEE.STD_LOGIC_1164.ALL;
实体comp1是
端口(a:标准_逻辑中;
b:标准逻辑;
g:标准逻辑;
l:在标准逻辑中;
e:标准逻辑;
伟大:走出标准逻辑;
减:输出标准逻辑;
相等:输出标准(U逻辑);
结束;
comp1的架构comp1是
信号s1、s2、s3:标准_逻辑;
开始
s1 b_32,
g_32=>g_32,
l_32=>l_32,
e_32=>e_32
);
刺激程序:过程
开始
a_32您将链接信号向后,并且第一个输入要显示相等:
architecture comp32_arch of comp32 is
component comp1
port (a,b,g,l,e : in std_logic ;
great,less,equal : out std_logic);
end component comp1;
signal gre : std_logic_vector(BW downto 0);
signal les : std_logic_vector(BW downto 0);
signal equ : std_logic_vector(BW downto 0);
begin
gre(BW) <= '0'; -- gre(0) <= '0';
les(BW) <= '0'; -- les(0) <= '0';
equ(BW) <= '1'; -- equ(0) <= '0';
gen:
for i in 0 to BW-1 generate
biti:
comp1
port map (
a => a_32(i),
b => b_32(i),
g => gre(i+1), -- gre(i),
l => les(i+1), -- les(i),
e => equ(i+1), -- equ(i),
great => gre(i), -- gre(i+1),
less => les(i), -- les(i+1),
equal => equ(i) -- equ(i+1)
);
end generate;
g_32 <= gre(0); -- gre(BW);-- (BW-1);
l_32 <= les(0); -- les(BW); -- (BW-1);
e_32 <= equ(0); -- equ(BW); -- (BW-1);
end architecture comp32_arch;
架构comp32\u comp32的架构是
组件组件1
端口(a、b、g、l、e:标准逻辑中;
大、小、相等:输出标准逻辑);
端部组件comp1;
信号gre:标准逻辑向量(BW降至0);
信号les:标准逻辑向量(BW降到0);
信号等式:标准逻辑向量(BW降至0);
开始
gre(BW)gre(i),--gre(i+1),
减=>les(i),--les(i+1),
equal=>equal(i)——equal(i+1)
);
终端生成;
谢谢你帮助我!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY comp32 is
GENERIC (BW : INTEGER :=32);
PORT ( a_32 : IN STD_LOGIC_VECTOR (BW -1 DOWNTO 0);
b_32 : IN STD_LOGIC_VECTOR (BW -1 DOWNTO 0);
g_32 : OUT STD_LOGIC ;
l_32 : OUT STD_LOGIC ;
e_32 : OUT STD_LOGIC );
END comp32;
ARCHITECTURE comp32_arch OF comp32 IS
COMPONENT comp1
PORT (a,b,g,l,e : IN std_logic ;
great,less,equal : OUT std_logic);
END COMPONENT comp1;
signal gre : std_logic_vector(BW downto 0);
signal les : std_logic_vector(BW downto 0);
signal equ : std_logic_vector(BW downto 0);
begin
gre(0)<='0';les(0)<='0';equ(0)<='0';
gen: for i in 0 to BW-1 generate
biti: comp1 port map( a => a_32(i),b => b_32(i), g => gre(i), l => les(i), e =>equ(i),
great => gre(i+1), less => les(i+1), equal => equ(i+1));
end generate;
g_32 <= gre(BW-1);
l_32 <= les(BW-1);
e_32 <= equ(BW-1);
end comp32_arch;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY comp32_TB IS
END comp32_TB;
ARCHITECTURE behavior OF comp32_TB IS
COMPONENT comp32
PORT(
a_32 : IN std_logic_vector(31 downto 0);
b_32 : IN std_logic_vector(31 downto 0);
g_32 : OUT std_logic;
l_32 : OUT std_logic;
e_32 : OUT std_logic
);
END COMPONENT;
signal a_32 : std_logic_vector(31 downto 0) := (others => '0');
signal b_32 : std_logic_vector(31 downto 0) := (others => '0');
signal g_32 : std_logic;
signal l_32 : std_logic;
signal e_32 : std_logic;
BEGIN
uut: comp32 PORT MAP (
a_32 => a_32,
b_32 => b_32,
g_32 => g_32,
l_32 => l_32,
e_32 => e_32
);
stim_proc: process
begin
a_32 <="00000000000000000000000000000000";b_32<="00000000000000000000000000000000";wait for 1500 ns;
a_32 <="00000000000000000000000000000001";b_32<="00000000000000000000000000000000";wait for 1500 ns;
a_32 <="00000000000000000000000000000000";b_32<="10000000000000000000000000000000";wait for 1500 ns;
wait;
end process;
END;
architecture comp32_arch of comp32 is
component comp1
port (a,b,g,l,e : in std_logic ;
great,less,equal : out std_logic);
end component comp1;
signal gre : std_logic_vector(BW downto 0);
signal les : std_logic_vector(BW downto 0);
signal equ : std_logic_vector(BW downto 0);
begin
gre(BW) <= '0'; -- gre(0) <= '0';
les(BW) <= '0'; -- les(0) <= '0';
equ(BW) <= '1'; -- equ(0) <= '0';
gen:
for i in 0 to BW-1 generate
biti:
comp1
port map (
a => a_32(i),
b => b_32(i),
g => gre(i+1), -- gre(i),
l => les(i+1), -- les(i),
e => equ(i+1), -- equ(i),
great => gre(i), -- gre(i+1),
less => les(i), -- les(i+1),
equal => equ(i) -- equ(i+1)
);
end generate;
g_32 <= gre(0); -- gre(BW);-- (BW-1);
l_32 <= les(0); -- les(BW); -- (BW-1);
e_32 <= equ(0); -- equ(BW); -- (BW-1);
end architecture comp32_arch;