Vhdl 使用1位ALU制作16位ALU
你好，我正在尝试从几个1位ALU创建一个16位ALU 我创建了一个名为basic_alu1的包，其中包含一个1位ALU组件。代码如下：Vhdl 使用1位ALU制作16位ALU,vhdl,alu,Vhdl,Alu,你好，我正在尝试从几个1位ALU创建一个16位ALU 我创建了一个名为basic_alu1的包，其中包含一个1位ALU组件。代码如下： library ieee; use ieee.std_logic_1164.all; package basic_alu1 is component alu1 port (a, b: std_logic_vector(1 downto 0); m: in std_logic_vector(1 downto 0);
library ieee;
use ieee.std_logic_1164.all;
package basic_alu1 is
component alu1
port (a, b: std_logic_vector(1 downto 0);
m: in std_logic_vector(1 downto 0);
result: out std_logic_vector(1 downto 0));
end component;
end package basic_alu1;
library ieee;
use ieee.std_logic_1164.all;
entity alu1 is
port (a, b: std_logic_vector(1 downto 0);
m: in std_logic_vector(1 downto 0);
result: out std_logic_vector(1 downto 0));
end alu1;
architecture arch1 of alu1 is
begin
process(a, b, m)
begin
case m is
when "00" =>
result <= a + b;
when "01" =>
result <= a + (not b) + 1;
when "10" =>
result <= a and b;
when "11" =>
result <= a or b;
end case
end process
end arch1
下面是一个如何创建N位加法器组件的示例。首先，您需要创建一个全加器，这是一个也考虑进位的加法器
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fullAdder IS
PORT (a : IN STD_LOGIC;
b : IN STD_LOGIC;
cin : IN STD_LOGIC;
y : OUT STD_LOGIC;
cout : OUT STD_LOGIC);
END fullAdder;
ARCHITECTURE arch_fullAdder OF fullAdder IS
BEGIN
y <= a XOR b XOR cin;
cout <= (a AND b) OR
(b AND cin) OR
(a AND cin);
END arch_fullAdder;
ieee库；
使用ieee.std_logic_1164.ALL；
实体全加器是
端口（a：标准_逻辑中；
b：标准逻辑；
cin：标准逻辑；
y：输出标准逻辑；
cout：输出标准逻辑）；
端全加器；
全加器的架构是arch_全加器
开始
y b(N),，
cin=>进位（N），
y=>y_温度（N），
cout=>进位（N+1）；
终端生成；
进位（0）‘0’；
Outs:OUT标准_逻辑_向量（宽度-1到0））；
末端ALU；
ALU的建筑arch_ALU是
元件纹波加法器
端口（a:STD_逻辑_向量中（宽度-1到0）；
b：标准逻辑向量（宽度-1到0）；
cin：在标准逻辑中：='0'；
y：输出标准逻辑向量（宽度-1到0）；
cout：输出标准逻辑）；
端部元件；
信号RCA_输出：标准逻辑_向量（宽度-1向下至0）：=（其他=>'0'）；
信号B_neg:STD_逻辑_向量（宽度-1到0）：=（其他=>'0'）；
信号c_标志：标准_逻辑：='0'；
信号c_reg:STD_逻辑：='0'；
信号cin:STD_逻辑：='0'；
开始
RCA_comp:ripple_加法器
端口映射（a=>a，
b=>b_负，
Cin=>Cin，
y=>RCA_输出，
Cout=>c_标志）；
使用Op SELECT
这是一个半加法器：结果你的代码不是一个加法器。它也有各种语法错误，您的问题不清楚-什么计数器？正如Matthew所指出的，没有进位链的16位ALU是无法构建的。除了大量缺少的分号、缺少的end语句、声明为单个std_逻辑的result_x4以及缺少的case others选项之外，没有“+”运算符重载用于向std_逻辑值添加抽象文字。为什么要用1位ALU构造16位ALU？这是一个类赋值吗？Charles Steinkuehler的回答（）提到“暂时忽略进位问题，您通常只需设置一个for generate循环并实例化多个按位逻辑副本，可能是第一个和/或最后一个元素的特殊大小写”，警告读者进位未涵盖，他显示了result\u x4（bitindex））
表示结果为数组值的选定名称。
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fullAdder IS
PORT (a : IN STD_LOGIC;
b : IN STD_LOGIC;
cin : IN STD_LOGIC;
y : OUT STD_LOGIC;
cout : OUT STD_LOGIC);
END fullAdder;
ARCHITECTURE arch_fullAdder OF fullAdder IS
BEGIN
y <= a XOR b XOR cin;
cout <= (a AND b) OR
(b AND cin) OR
(a AND cin);
END arch_fullAdder;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ripple_adder IS
GENERIC (WIDTH : NATURAL := 32);
PORT(a : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
cin : IN STD_LOGIC := '0';
y : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
cout : OUT STD_LOGIC);
END ripple_adder;
ARCHITECTURE arch_ripple_adder OF ripple_adder IS
SIGNAL carry : STD_LOGIC_VECTOR(WIDTH DOWNTO 0);
SIGNAL y_temp : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
COMPONENT fullAdder IS
PORT(a : IN STD_LOGIC;
b : IN STD_LOGIC;
cin : IN STD_LOGIC;
y : OUT STD_LOGIC;
cout : OUT STD_LOGIC);
END COMPONENT;
BEGIN
N_bit_adder_generate : FOR N IN 0 TO WIDTH-1 GENERATE
N_bit_adder : fullAdder
PORT MAP(a => a(N),
b => b (N),
cin => carry(N),
y => y_temp(N),
cout => carry(N + 1));
END GENERATE;
carry(0) <= cin;
cout <= carry(WIDTH);
y <= y_temp;
END arch_ripple_adder;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ALU IS
GENERIC(WIDTH : NATURAL := 32);
PORT(Clk : IN STD_LOGIC := '0';
Reset : IN STD_LOGIC := '0';
A : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (OTHERS => '0');
B : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (OTHERS => '0');
Op : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
Outs : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0));
END ALU;
ARCHITECTURE arch_ALU OF ALU IS
COMPONENT ripple_adder
PORT(a : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
cin : IN STD_LOGIC := '0';
y : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
cout : OUT STD_LOGIC);
END COMPONENT;
SIGNAL RCA_output : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL B_neg : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL c_flag : STD_LOGIC := '0';
SIGNAL c_reg : STD_LOGIC := '0';
SIGNAL cin : STD_LOGIC := '0';
BEGIN
RCA_comp : ripple_adder
PORT MAP(a => A,
b => B_neg,
Cin => cin,
y => RCA_output,
Cout => c_flag);
WITH Op SELECT
B_neg <= NOT(B) WHEN "1000",
B WHEN OTHERS;
WITH Op SELECT
cin <= '1' WHEN "1000", -- SUB
c_reg WHEN "0111", -- ADDC
'0' WHEN OTHERS; -- ADD/ADDS
ALU_Process:
PROCESS(Clk, Reset)
BEGIN
IF Reset = '0' THEN
Outs <= (OTHERS => '0');
c_reg <= '0';
ELSIF rising_edge(Clk) THEN
CASE Op IS
WHEN "0001" => Outs <= A AND B;
WHEN "0010" => Outs <= A OR B;
WHEN "0011" => Outs <= A NOR B;
WHEN "0100" => Outs <= A XOR B;
WHEN "0101" => Outs <= RCA_output; -- ADD
WHEN "0110" => Outs <= RCA_output; -- ADDS
c_reg <= c_flag;
WHEN "0111" => Outs <= RCA_output; -- ADDC
WHEN "1000" => Outs <= RCA_output; -- SUB
WHEN "1001" => Outs <= STD_LOGIC_VECTOR(UNSIGNED(A) SLL to_integer(UNSIGNED(B(4 DOWNTO 0))));
WHEN "1010" => Outs <= STD_LOGIC_VECTOR(unsigned(A) SRL to_integer(UNSIGNED(B(4 DOWNTO 0))));
WHEN "1011" => Outs <= STD_LOGIC_VECTOR(shift_right(SIGNED(A),to_integer(UNSIGNED(B(4 DOWNTO 0)))));
WHEN OTHERS => Outs <= (OTHERS => '0');
END CASE;
END IF;
END PROCESS;
END arch_ALU;