Vhdl 同步反问题

我在同步计数器的一些VHDL代码中遇到了一个计时问题。我不明白为什么计数器以一个时钟脉冲前进两次。我尝试了一切，包括在D触发器中添加不必要的代码，以使其正常工作。这是一个类，我们必须使用自己的模型，而不是库块。我是一名参加本课程的软件程序员，有时会遇到“即时”作业而不是程序中的“串行”作业

如果有人能给我指出正确的方向，我将不胜感激。多谢各位

--D-FlipFlop

ENTITY D_flipflop IS 
  PORT ( D, Clock, Reset : IN STD_LOGIC ; 
                Q : OUT STD_LOGIC) ; 
END D_flipflop ;

ARCHITECTURE Behavior OF D_flipflop IS 

Signal Q_buff : STD_LOGIC := '0';

BEGIN
  Q <= Q_buff;

  PROCESS ( Clock, Reset ) 
  BEGIN
    IF (Reset = '0') THEN
      Q_buff <= '0';
    ElSE
      IF RISING_EDGE(Clock) THEN 
        IF (D = '1') THEN  -- Was D <=Q changed as a trial fix
           Q_buff <= '1';
        ELSE
           Q_buff <= '0';
        END IF;
      END IF;               
    END IF ; 
  END PROCESS ; 
END Behavior ; 

--4 bit Synchronous counter with load
entity SyncCounter is
  Port ( CLOCK : in  STD_LOGIC;
             D : in  STD_LOGIC_VECTOR (3 downto 0);
             Q : inout STD_LOGIC_VECTOR (3 downto 0);
            CE : in STD_LOGIC;
          Load : in STD_LOGIC;
           CEO : out STD_LOGIC;
         Reset : in  STD_LOGIC);
end SyncCounter;



architecture Behavioral of SyncCounter is

SIGNAL ND0, ND1, ND2, ND3, CE_CLOCK : STD_LOGIC := '0';

component D_flipflop IS 
  PORT ( D, CLOCK, RESET : IN STD_LOGIC ; 
         Q : OUT STD_LOGIC) ; 
END component ;

begin

CE_CLOCK <=  (CLOCK and (CE or Load));

ND0 <= (NOT Q(0) and NOT Load) 
    or (D(0) and Load);

SC_D0: D_flipflop PORT MAP ( ND0, CE_CLOCK, Reset, Q(0));

ND1 <= (((NOT Q(0) AND Q(1)) OR (Q(0) AND NOT Q(1))) and NOT LOAD)  -- (Q(0) XOR Q(1))
 or (D(1) and Load); 

SC_D1: D_flipflop PORT MAP ( ND1, CE_CLOCK, Reset, Q(1));

ND2 <= (((Q(0) and Q(1) and NOT Q(2)) or (Q(2) and (NOT Q(0) or NOT Q(1)))) AND NOT Load)
    or (D(2) and Load);

SC_D2: D_flipflop PORT MAP ( ND2, CE_CLOCK, Reset, Q(2));

ND3 <= ((((NOT Q(0) or NOT Q(1) or NOT Q(2)) AND Q(3)) OR (Q(0) and Q(1) and Q(2) and NOT Q(3))) AND NOT Load)
    or (D(3) and Load);

SC_D3: D_flipflop PORT MAP ( ND3, CE_CLOCK, Reset, Q(3));

CEO <=  Q(0) AND Q(1) AND Q(2) AND Q(3) AND CE;  --- CEO output

end Behavioral;

——D触发器
实体D_触发器为
端口（D，时钟，复位：在标准逻辑中；
Q：输出标准（U逻辑）；
结束D_触发器；
D_触发器的架构行为是
信号Q_buff:STD_逻辑：='0'；
开始
Q这个问题可能是由于时钟上的逻辑造成的
CE\u clock莫顿的答案并不是全部

与Morten的答案一致——使用enables，将计数器中的D FF视为具有输入多路复用器，其术语为保持（Q）、切换（而非Q）和加载（D）

在本例中，等效多路复用器如cntdin所示：

library ieee;
use ieee.std_logic_1164.all;

entity cntr4 is
    port (
        d:          in  std_logic_vector (3 downto 0);
        load:       in  std_logic;
        reset:      in  std_logic;
        enable:     in  std_logic;
        clk:        in  std_logic;
        q:          out std_logic_vector (3 downto 0);
        enab_out:   out std_logic
    );
end ;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
    port (
        d:      in  std_logic;
        clk:    in  std_logic;
        q:      out std_logic
    );
end entity;

architecture behave of dff is

begin
    process(clk)
    begin
        if rising_edge(clk) then
            q <= d;
        end if;
    end process;
end architecture;

architecture struct of cntr4 is

    component dff is
        port (
            d:      in  std_logic;
            clk:    in  std_logic;
            q:      out std_logic
        );
    end component;

    signal cntincr,cntd,cntq: std_logic_vector (q'range);

    begin

cnt_incr:         -- incrementer
    process(cntq)   
    begin
        cntincr(0) <= not cntq(0);
        cntincr(1) <= cntq(1) xor cntq(0);
        cntincr(2) <= cntq(2) xor (cntq(0) and cntq(1));
        cntincr(3) <= cntq(3) xor (cntq(0) and cntq(1) and cntq(2));
    end process;

cntdin:
    for i in cntd'range generate
        cntd(i) <= (cntq(i)    and not reset and not enable) or
                   (d(i)       and not reset and     enable and     load) or
                   (cntincr(i) and not reset and     enable and not load);
    end generate;

cntreg:
    for i in cntq'range generate
        D_FF: dff 
            port map (
                d => cntd(i),
                clk => clk,
                q => cntq(i)
            );
    end generate;

cntptr:
    q <= cntq;

en_out:
    enab_out <= enable and cntq(0) and cntq(1) and cntq(2) and cntq(3);    

end architecture;

ieee库；
使用ieee.std_logic_1164.all；
实体cntr4是
港口(
d：标准逻辑向量（3到0）；
负载：在标准逻辑中；
复位：在标准逻辑中；
启用：在std_逻辑中；
clk：标准逻辑中；
q：输出标准逻辑向量（3到0）；
enab_out：out标准_逻辑
);
结束；
图书馆ieee；
使用ieee.std_logic_1164.all；
实体dff是
港口(
d：在标准逻辑中；
clk：标准逻辑中；
q：输出标准逻辑
);
终端实体；
dff的体系结构表现为
开始
过程（clk）
开始
如果上升沿（clk），则
Q
library ieee;
use ieee.std_logic_1164.all;

entity cntr4 is
    port (
        d:          in  std_logic_vector (3 downto 0);
        load:       in  std_logic;
        reset:      in  std_logic;
        enable:     in  std_logic;
        clk:        in  std_logic;
        q:          out std_logic_vector (3 downto 0);
        enab_out:   out std_logic
    );
end ;

library ieee;
use ieee.std_logic_1164.all;

entity dff is
    port (
        d:      in  std_logic;
        clk:    in  std_logic;
        q:      out std_logic
    );
end entity;

architecture behave of dff is

begin
    process(clk)
    begin
        if rising_edge(clk) then
            q <= d;
        end if;
    end process;
end architecture;

architecture struct of cntr4 is

    component dff is
        port (
            d:      in  std_logic;
            clk:    in  std_logic;
            q:      out std_logic
        );
    end component;

    signal cntincr,cntd,cntq: std_logic_vector (q'range);

    begin

cnt_incr:         -- incrementer
    process(cntq)   
    begin
        cntincr(0) <= not cntq(0);
        cntincr(1) <= cntq(1) xor cntq(0);
        cntincr(2) <= cntq(2) xor (cntq(0) and cntq(1));
        cntincr(3) <= cntq(3) xor (cntq(0) and cntq(1) and cntq(2));
    end process;

cntdin:
    for i in cntd'range generate
        cntd(i) <= (cntq(i)    and not reset and not enable) or
                   (d(i)       and not reset and     enable and     load) or
                   (cntincr(i) and not reset and     enable and not load);
    end generate;

cntreg:
    for i in cntq'range generate
        D_FF: dff 
            port map (
                d => cntd(i),
                clk => clk,
                q => cntq(i)
            );
    end generate;

cntptr:
    q <= cntq;

en_out:
    enab_out <= enable and cntq(0) and cntq(1) and cntq(2) and cntq(3);    

end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity cntr4_tb is
end entity;

architecture foo of cntr4_tb is

    signal d:          std_logic_vector (3 downto 0);
    signal load:       std_logic;
    signal reset:      std_logic;
    signal enable:     std_logic;
    signal clk:        std_logic := '1';
    signal q:          std_logic_vector (3 downto 0);
    signal enab_out:   std_logic;
    signal reset_not:  std_logic;

begin

    reset_not <= not reset;

DUT:
    entity 
    work.SyncCounter
        port map (
                CLOCK => clk,
                D => d,
                Q => q,
                CE => enable,
                Load => load,
                Reset => reset_not,
                CEO => enab_out
        );

CLOCK:
    process
    begin
        wait for 10 ns;
        clk <= not clk;
        if Now > 720 ns then
            wait;
        end if;
    end process;

STIMULUS:
    process
    begin
        wait for 10 ns;
        reset <= '1';
        load <= '0';
        d <=  X"5";
        enable <= '0';
        wait for 30 ns;
        reset <= '0';
        wait for 30 ns;
        load <= '1';
        enable <= '1';
        wait for 20 ns;
        load <= '0';
        enable <= '0';
        wait for 20 ns;
        enable <= '1';
        wait for 80 ns;
        enable <= '0';
        wait for 20 ns;
        enable <= '1';
        wait;

    end process;
end architecture;

-- CE_CLOCK <=  (CLOCK and (CE or Load));

   CE_CLOCK <= CLOCK or  not (CE or Load);