Vhdl Xilinx/ISim似乎声称其值为X,但它已被声明
我刚刚开始学习如何使用这个工具,所以如果我的问题看起来很愚蠢,我会提前道歉。我已经在许多论坛上搜索了这个错误(已经回复了帖子,不是我的),无法理解我做错了什么,所以这里是我的问题: 我的行为准则:Vhdl Xilinx/ISim似乎声称其值为X,但它已被声明,vhdl,xilinx,xilinx-ise,Vhdl,Xilinx,Xilinx Ise,我刚刚开始学习如何使用这个工具,所以如果我的问题看起来很愚蠢,我会提前道歉。我已经在许多论坛上搜索了这个错误(已经回复了帖子,不是我的),无法理解我做错了什么,所以这里是我的问题: 我的行为准则: ----------------------------------------------------------------------------- ----- -- Company: -- Engineer: -- -- Create Date: 01:47:22 07/07
----------------------------------------------------------------------------- -----
-- Company:
-- Engineer:
--
-- Create Date: 01:47:22 07/07/2015
-- Design Name:
-- Module Name: Module_1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------- -----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned valuessss
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Module_1 is
port (A,B,WE,reset : in std_logic;
clk : in std_logic;
DIN : in signed(3 downto 0);
FULL,EMPTY,ERROR : out std_logic:= '0';
PARKFREE : out signed(3 downto 0)
);
end Module_1;
architecture Behavioral of Module_1 is
signal current_state,next_state:std_ulogic_vector(1 downto 0);
signal empty_bf, full_bf :std_ulogic;
signal enter, reset_b : std_ulogic := '0' ;
constant s0: std_ulogic_vector (1 downto 0):="00";
constant s1: std_ulogic_vector (1 downto 0):="10";
constant s2: std_ulogic_vector (1 downto 0):="11";
constant s3: std_ulogic_vector (1 downto 0):="01";
signal park_counter,buffr: signed(3 downto 0):="0000";
signal PARKTOTAL,free_park_counter: signed(3 downto 0):= "1111";
begin
p1: process (clk,reset,reset_b)
begin
if (reset = '1') then
current_state <= s0;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process p1;
p2: process (current_state,A,B)
begin
next_state <= current_state;
case current_state is
when s0 =>
if A = '1' then
enter <= '1';
next_state <= s1;
elsif B = '1' then
next_state <= s3;
end if;
when s1 =>
if A = '0' then
enter <= '0';
next_state <= s0;
elsif B = '1' then
next_state <= s2;
end if;
when s2 =>
if A = '0' then
next_state <= s3;
elsif B = '0' then
next_state <= s1;
end if;
when s3 =>
if B = '0' then
enter <= '0';
next_state <= s0;
elsif A = '1' then
next_state <= s2;
end if;
when others =>
end case;
end process p2;
p3: process(current_state,A,B)
begin
case current_state is
when s1 =>
if enter = '0' and A = '0' and empty_bf = '0' then
park_counter <= park_counter - 1;
free_park_counter <= free_park_counter + 1;
ERROR <= '0';
end if;
when s3 =>
if enter = '1' and B = '0' and full_bf = '0' then
park_counter <= park_counter + 1;
free_park_counter <= free_park_counter - 1;
ERROR <= '0';
end if;
when others =>
end case;
end process p3;
max: process(WE)
begin
if clk'event and clk = '1' and WE = '1' then
PARKTOTAL <= DIN ;
buffr <= DIN ;
if (free_park_counter < buffr - park_counter) then
ERROR <= '1';
reset_b <= '1';
else free_park_counter <= buffr - park_counter;
end if;
end if;
end process max;
incr: process(free_park_counter,DIN)
begin
PARKFREE <= free_park_counter;
if (free_park_counter = 15) then
EMPTY <= '1';
empty_bf <= '1';
else EMPTY <= '0';
empty_bf <= '0';
end if;
if (free_park_counter = 0) then
FULL <= '1';
full_bf <= '1';
else FULL <= '0';
full_bf <= '0';
end if;
end process incr;
end Behavioral;
--------------------------------------------------------------------------------------------
--公司:
--工程师:
--
--创建日期:01:47:22 07/07/2015
--设计名称:
--模块名称:模块_1-行为
--项目名称:
--目标设备:
--工具版本:
--说明:
--
--依赖项:
--
--修订:
--版本0.01-已创建文件
--补充意见:
--
----------------------------------------------------------------------------- -----
图书馆IEEE;
使用IEEE.STD_LOGIC_1164.ALL;
使用IEEE.STD_LOGIC_ARITH.ALL;
使用IEEE.STD_LOGIC_UNSIGNED.ALL;
--如果使用,请取消注释以下库声明
--带符号或无符号值的算术函数sss
--使用IEEE.NUMERIC_STD.ALL;
--如果正在实例化,请取消对以下库声明的注释
--此代码中的任何Xilinx原语。
--UNISIM图书馆;
--使用UNISIM.VComponents.all;
实体模块_1为
端口(A、B、WE、reset):在std_逻辑中;
clk:标准逻辑中;
DIN:已签名(3到0);
满、空、错误:out std_逻辑='0';
驻车自由:已签出(3到0)
);
终端模块_1;
模块_1的架构是
信号当前状态,下一状态:标准逻辑向量(1到0);
信号空载、满载:标准逻辑;
信号输入,复位:标准逻辑:='0';
常数s0:std_ulogic_向量(1到0):=“00”;
常数s1:std_ulogic_向量(1到0):=“10”;
常数s2:std_ulogic_向量(1到0):=“11”;
常数s3:std_ulogic_向量(1到0):=“01”;
信号驻车计数器,buffer:已签名(3到0):=“0000”;
信号停车总计,自由停车计数器:签名(3到0):=“1111”;
开始
p1:过程(时钟、复位、复位)
开始
如果(重置='1'),则
当前状态在ISim中,如果您浏览左侧的树菜单,您可以将所需的任何内部信号添加到then signals窗口。将所有信号相加,重新运行模拟并查找具有“U”|“X”|“W”|“Z”|“-”值的信号。这应该给我们找到问题的线索
如果您真的不熟悉VHDL,我的这个答案应该可以帮助您理解这种描述语言的一些基本概念:)
另一个建议是我用艰苦的方式学到的,但你可以在我们解决这个问题后再考虑:教科书甚至Xilinx描述了如何用两个甚至三个不同的进程实现有限状态机。这来自一种教育方法,其中FSM在同步逻辑和异步逻辑中被划分。实际上,这弊大于利:大多数FSM都可以用一个同步进程来描述。谷歌搜索它(或者如果你感兴趣,我们可以讨论一下)并尝试一下,你会很快掌握它的窍门,它会真正简化代码(你甚至不再需要两个单独的状态信号!)。问题标题中有些混乱:声明信号和设置信号值是完全独立的
初始化信号(在声明中)将影响其值,但不能完全确定它。如果初始化和另一个驱动值不同,结果可能为“X”。同样,如果信号是由不同的过程驱动的,而这些过程对其值不一致
现在,您正在使用状态机的多进程形式,其中操作在时钟进程和组合进程之间进行分割。这些都是由不止一本教科书推荐的。这是不幸的,因为众所周知,它们很难得到正确的结果,例如,片刻的检查将表明过程P3上的灵敏度列表是错误的
修复P3的灵敏度列表可能不会影响问题,因为P3也会在组合回路中驱动自己的输入。考虑到,如果进程在其敏感列表中的组合输入上出现故障多次唤醒,则添加将发生几次…
以单时钟过程P1的形式重写这三个过程(不幸的是,这在几本教科书中没有很好地教授)将避免所有这些困难。根据Brian的回答,您的设计是不可行的。您的测试台在时钟边缘之前从s3或s1到s0时产生消息。免费停车柜台转到'U'
s。(一旦它得到U'
s,它就不会进一步循环,没有信号值变化就不会发生任何事件)
你的计数器应该计时,以防止组合循环,另外,由于组合延迟不均匀,它们可能无法有效地合成时钟。灵敏度列表同样应完整,如果没有其他原因,只是为了使模拟与合成结果相匹配
查看测试台的结果:
(可点击)
我们可以将其与Synopsys软件包std_logic_arith中的算术运算符的消息进行比较:
../../../src/synopsys/std_logic_arith.vhdl:315:20:@350ns:(断言警告):算术操作数中有一个“U”|“X”|“W”|“Z”|“-”,结果将是“X”(es)。
../../../src/synopsys/std_logic_arith.vhdl:315:20:@350ns:(断言警告):算术操作数中有一个“U”|“X”|“W”|“Z”|“-”,结果将是“X”(es)。
../../../src/synopsys/std_logic_arith.vhdl:315:20:@550ns:(断言警告):算术操作数中有一个“U”|“X”|“W”|“Z”|“-”,结果将是“X”(es)
波形中显示的信号是按照重要性和外观的顺序选择的,我们会立即看到在空闲\U驻车计数器上得到'U'
s以及错误
----------------------------------------------------------------------------- ---
-- Company:
-- Engineer:
--
-- Create Date: 02:17:07 07/11/2015
-- Design Name:
-- Module Name: D:/Users/ErgasiaFPGA/Testbench.vhd
-- Project Name: ErgasiaFPGA
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Module_1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Testbench IS
END Testbench;
ARCHITECTURE behavior OF Testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Module_1
PORT(
A : IN std_logic;
B : IN std_logic;
WE : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
DIN : IN signed(3 downto 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic;
ERROR : OUT std_logic;
PARKFREE : OUT signed(3 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal WE : std_logic := '0';
signal reset : std_logic := '0';
signal clk : std_logic := '0';
signal DIN : signed(3 downto 0) := (others => '0');
--Outputs
signal FULL : std_logic;
signal EMPTY : std_logic;
signal ERROR : std_logic;
signal PARKFREE : signed(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Module_1 PORT MAP (
A => A,
B => B,
WE => WE,
reset => reset,
clk => clk,
DIN => DIN,
FULL => FULL,
EMPTY => EMPTY,
ERROR => ERROR,
PARKFREE => PARKFREE
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1' ;
wait for 100 ns;
reset <= '0' ;
wait for clk_period*10;
-- insert stimulus here
A <= '1' ;
wait for clk_period*5;
B <= '1' ;
wait for clk_period*5;
A <= '0' ;
wait for clk_period*5;
B <= '0' ;
wait for clk_period*5;
B <= '1' ;
wait for clk_period*5;
A <= '1' ;
wait for clk_period*5;
B <= '0' ;
wait for clk_period*5;
A <= '0' ;
wait;
end process;
END;
p3: process(current_state,A,B)
begin
case current_state is
when s1 =>
if enter = '0' and A = '0' and empty_bf = '0' then
park_counter <= park_counter - 1;
free_park_counter <= free_park_counter + 1;
ERROR <= '0';
end if;
when s3 =>
if enter = '1' and B = '0' and full_bf = '0' then
park_counter <= park_counter + 1;
free_park_counter <= free_park_counter - 1;
ERROR <= '0';
end if;
when others =>
end case;
end process p3;