Compiler errors verilog中的并发分配错误

我的代码如下：

   module trapverilog(
        input CLK,
        input SIGNALP,
         input SIGNAL1,
         input SIGNAL2,
         input SIGNAL3,
         input SIGNAL4,
         input SIGNAL5,
         input SIGNAL6,
         input SIGNAL7,
         input X1,
         input X2,
         input X3,
         input X4,
         input X5,
         input X6,
         input X7,
         input SUMP,
         input SUM1,
         input SUM2,
         input SUM3,
         input SUM4,
         input SUM5,
         input SUM6,
         input SUM7, // OUT pins are mapped to SUM pins on board
        output reg OUTP,
         output reg OUT1,
         output reg OUT2,
         output reg OUT3,
         output reg OUT4,
         output reg OUT5,
         output reg OUT6,
         output reg OUT7
        );

reg[6:0] yregone;
reg[6:0] yregtwo;
reg[6:0] sum;
reg[6:0] SUM;
assign SUM = {SUM1, SUM2, SUM3, SUM4, SUM5, SUM6, SUM7};
reg[7:0] SIGNAL;
assign SIGNAL = {SIGNAL1, SIGNAL2, SIGNAL3, SIGNAL4, SIGNAL5, SIGNAL6, SIGNAL7};
reg[6:0] x;
assign x = {X1. X2. X3. X4. X5, X6, X7};

always @(posedge CLK)
begin
    if (SIGNALP == 1)
    begin
        SIGNAL = SIGNAL * -1;
    end

    if (SUMP == 1)
    begin
        SUM = SUM * -1;
    end

    yregtwo = yregone;
    yregone = SIGNAL;

    if (yregtwo != 0)
    begin
        sum = ((yregone + yregtwo)*x/2) + SUM; //treats x as plain h, change if treated as h/2

        if (sum < 0)
        begin
            OUTP = 1;
        end

        OUT1 = sum[1];
        OUT2 = sum[2];
        OUT3 = sum[3];
        OUT4 = sum[4];
        OUT5 = sum[5];
        OUT6 = sum[6];
        OUT7 = sum[7];
    end
end

endmodule

它会产生错误

Target <SUM> of concurrent assignment or output port connection should be a net type.
Target <SIGNAL> of concurrent assignment or output port connection should be a net type.
Target <x> of concurrent assignment or output port connection should be a net type.

这些错误出现在定义信号、总和和x的行上。我相信问题的一部分是因为这些变量没有在always循环中定义，但是这样做会产生更多的错误。我能做些什么来解决这个问题

---

该代码是在verilog中实现梯形积分法的。大量的输入是因为我希望以并行方式而不是串行方式输入数据，因为这样速度更快。具有信号前缀的所有输入均用于信号变量，具有X前缀的所有输入均用于X变量，依此类推。输入名称末尾的P表示它是奇偶校验位。数字表示该位应该进入结果寄存器中的哪个点。

您正在多个位置分配这些信号。你不能那样做

assign SUM = {SUM1, SUM2, SUM3, SUM4, SUM5, SUM6, SUM7};
assign SIGNAL = {SIGNAL1, SIGNAL2, SIGNAL3, SIGNAL4, SIGNAL5, SIGNAL6, SIGNAL7};
....
if (SIGNALP == 1)
begin
    SIGNAL = SIGNAL * -1;
end

if (SUMP == 1)
begin
    SUM = SUM * -1;
etc.

关于X：

assign x = {X1. X2. X3. X4. X5, X6, X7};
              ^   ^   ^   ^  Full stop????

---

此外，您还应在always@posedge CLK部分使用非阻塞作业。

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