Debugging 连续赋值中的语法错误
我的代码中的错误在哪里Debugging 连续赋值中的语法错误,debugging,syntax,verilog,Debugging,Syntax,Verilog,我的代码中的错误在哪里 module mikroislemci(data1,data2,opcode,data_out,flag); input [7:0] data1; input [7:0] data2; input [3:0] opcode; output [7:0] data_out; output [4:0] flag; wire [8:0] tmp; wire [7:0] tmp1; if(opcode==4'b0000) begin if (data1==data2)
module mikroislemci(data1,data2,opcode,data_out,flag);
input [7:0] data1;
input [7:0] data2;
input [3:0] opcode;
output [7:0] data_out;
output [4:0] flag;
wire [8:0] tmp;
wire [7:0] tmp1;
if(opcode==4'b0000)
begin
if (data1==data2)
begin
assign flag[0]=1;
end
else
begin
assign tmp = data1+data2;
assign data_out=tmp [7:0];
assign flag[2]=tmp [8];
end
end
else if (opcode==4'b0001)
begin
if (data1==data2)
begin
assign flag[0]=1;
end
if(data1>data2)
begin
assign data_out=data1-data2;
end
else
begin
assign data_out=data2-data1;
assign flag[1]=1;
end
end
else if (opcode==4'b0010)
begin
assign data_out[0]=data1[0] and data2[0];
assign data_out[1]=data1[1] and data2[1];
assign data_out[2]=data1[2] and data2[2];
assign data_out[3]=data1[3] and data2[3];
assign data_out[4]=data1[4] and data2[4];
assign data_out[5]=data1[5] and data2[5];
assign data_out[6]=data1[6] and data2[6];
assign data_out[7]=data1[7] and data2[7];
end
else if (opcode==4'b0011)
begin
assign data_out[0]=data1[0] or data2[0];
assign data_out[1]=data1[1] or data2[1];
assign data_out[2]=data1[2] or data2[2];
assign data_out[3]=data1[3] or data2[3];
assign data_out[4]=data1[4] or data2[4];
assign data_out[5]=data1[5] or data2[5];
assign data_out[6]=data1[6] or data2[6];
assign data_out[7]=data1[7] or data2[7];
end
else if (opcode==4'b0100)
begin
assign data_out[0]=data1[0] xor data2[0];
assign data_out[1]=data1[1] xor data2[1];
assign data_out[2]=data1[2] xor data2[2];
assign data_out[3]=data1[3] xor data2[3];
assign data_out[4]=data1[4] xor data2[4];
assign data_out[5]=data1[5] xor data2[5];
assign data_out[6]=data1[6] xor data2[6];
assign data_out[7]=data1[7] xor data2[7];
end
else if (opcode==4'b0101)
begin
assign data_out[0]= not(data1[0]);
assign data_out[1]= not(data1[1]);
assign data_out[2]= not(data1[2]);
assign data_out[3]= not(data1[3]);
assign data_out[4]= not(data1[4]);
assign data_out[5]= not(data1[5]);
assign data_out[6]= not(data1[6]);
assign data_out[7]= not(data1[7]);
end
else if (opcode==4'b0110)
begin
if(data1==data2)
begin
assign flag[0]=1;
end
else if(data1<data2)
begin
assign flag[4]=0;
end
else if(data1>data2)
begin
assign flag[4]=1;
end
end
else if (opcode==4'b0111)
begin
assign data_out=data1<<data2;
end
else if (opcode==4'b1000)
begin
assign data_out=data1>>data2;
end
else
display("you entered wrong opcode try again");
endmodule
verilog if语句必须进入进程内部(初始或始终)
不要在这些进程中使用assign,而要使用reg或逻辑类型。上面创建了组合逻辑
要暗示顺序触发器,请使用:
always @(posedge clk) begin
flag[0] <= 1'b1;
end
再次使用reg或逻辑类型和非阻塞分配…输出到底是什么?data_out是输出。如果输出在加法器处为9位或在子标志处为负数,则可以使用cary或sign。这是我要做的工作谢谢你做了这么多finally@user220910很好,一旦你习惯了,Verilog也不算太坏。这不是最好的学习方法,但值得借鉴。
always @(posedge clk) begin
flag[0] <= 1'b1;
end