If statement VHDL if/else不可查找语法错误
所以我正在构建一个除法器,它将无符号8位数字除以53。它将商和余数显示为输出。我使用一个if/else语句来完成此任务。我在每个if/elseif/else语句附近发现语法错误,只是声明了一个语法错误,但我找不到错误,语法错误在哪里If statement VHDL if/else不可查找语法错误,if-statement,syntax,vhdl,If Statement,Syntax,Vhdl,所以我正在构建一个除法器,它将无符号8位数字除以53。它将商和余数显示为输出。我使用一个if/else语句来完成此任务。我在每个if/elseif/else语句附近发现语法错误,只是声明了一个语法错误,但我找不到错误,语法错误在哪里 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity divider is Port ( input : in STD_LOGIC_VECTOR (7 do
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity divider is
Port ( input : in STD_LOGIC_VECTOR (7 downto 0);
output : out STD_LOGIC_VECTOR (7 downto 0);
r : out STD_LOGIC_VECTOR ( 7 downto 0));
end divider;
architecture Behavioral of divider is
signal input : unsigned(7 downto 0);
signal n : unsigned(7 downto 0);
signal quotient : unsigned(7 downto 0);
signal remainder : unsigned(7 downto 0);
signal a : unsigned(7 downto 0);
signal b : unsigned(7 downto 0);
signal c : unsigned(7 downto 0);
signal d : unsigned(7 downto 0);
signal zero : unsigned(7 downto 0);
signal one : unsigned(7 downto 0);
signal two : unsigned(7 downto 0);
signal three : unsigned(7 downto 0);
signal four : unsigned(7 downto 0);
signal x : unsigned(7 downto 0);
signal y : unsigned(7 downto 0);
signal z : unsigned(7 downto 0);
signal t : unsigned(7 downto 0);
begin
a <= "11010100"; -- 212
b <= "110011111"; -- 159
c <= "01101010"; -- 106
d <= "00110101"; -- 53
zero <= "0000000"; -- 0
one <= "00000001"; -- 1
two <= "00000010"; -- 2
three <= "00000011"; -- 3
four <= "00000100"; -- 4
x <= n - a; -- input - 212
y <= n - b; -- input - 159
z <= n - c; -- input - 106
t <= n - d; -- input - 53
input <= n;
if (x > zero) then
quotient <= four;
remainder <= n - a;
elsif (y = zero) then
quotient <= three;
remainder <= n - b;
elsif (z > zero) then
quotient <= two;
remainder <= n - c;
elsif (t > zero) then
quotient <= one;
remainder <= n - d;
else
quotient <= zero;
remainder <= n;
end if;
output <= quotient;
r <= remainder;
end behavioral;
IEEE库;
使用IEEE.STD_LOGIC_1164.ALL;
使用ieee.numeric_std.all;
实体分隔符为
端口(输入:标准逻辑向量(7到0);
输出:输出标准逻辑向量(7到0);
r:输出标准逻辑向量(7到0);
端部分隔器;
行为分配器的结构是
信号输入:无符号(7到0);
信号n:无符号(7到0);
信号商:无符号(7到0);
信号余数:无符号(7到0);
信号a:无符号(7到0);
信号b:无符号(7到0);
信号c:无符号(7到0);
信号d:无符号(7到0);
信号零:无符号(7到0);
信号一:无符号(7到0);
信号二:无符号(7到0);
信号三:无符号(7到0);
信号四:无符号(7到0);
信号x:无符号(7到0);
信号y:无符号(7到0);
信号z:无符号(7到0);
信号t:无符号(7到0);
开始
a这分析了:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity divider is
port ( input: in std_logic_vector (7 downto 0);
output: out std_logic_vector (7 downto 0);
r: out std_logic_vector ( 7 downto 0)
);
end divider;
architecture behavioral of divider is
-- signal input: unsigned(7 downto 0);
signal n: unsigned(7 downto 0);
signal quotient: unsigned(7 downto 0);
signal remainder: unsigned(7 downto 0);
signal a: unsigned(7 downto 0);
signal b: unsigned(7 downto 0);
signal c: unsigned(7 downto 0);
signal d: unsigned(7 downto 0);
signal zero: unsigned(7 downto 0);
signal one: unsigned(7 downto 0);
signal two: unsigned(7 downto 0);
signal three: unsigned(7 downto 0);
signal four: unsigned(7 downto 0);
signal x: unsigned(7 downto 0);
signal y: unsigned(7 downto 0);
signal z: unsigned(7 downto 0);
signal t: unsigned(7 downto 0);
begin
a <= "11010100"; -- 212 -- get the lengths right
b <= "10011111"; -- 159 -- should these be constants?
c <= "01101010"; -- 106
d <= "00110101"; -- 53
zero <= "00000000"; -- 0
one <= "00000001"; -- 1
two <= "00000010"; -- 2
three <= "00000011"; -- 3
four <= "00000100"; -- 4
x <= n - a; -- input - 212
y <= n - b; -- input - 159
z <= n - c; -- input - 106
t <= n - d; -- input - 53
-- input <= n; -- can't assign inputs
process (x, zero, four, three, n, b, c, d) -- need a process
begin
if x > zero then
quotient <= four;
remainder <= n - a;
elsif y = zero then
quotient <= three;
remainder <= n - b;
elsif z > zero then
quotient <= two;
remainder <= n - c;
elsif t > zero then
quotient <= one;
remainder <= n - d;
else
quotient <= zero;
remainder <= n;
end if;
end process;
output <= std_logic_vector(quotient); -- need type conversion
r <= std_logic_vector(remainder); -- ditto
end architecture behavioral;
ieee库;
使用ieee.std_logic_1164.all;
使用ieee.numeric_std.all;
实体分隔符为
端口(输入:标准逻辑向量(7到0);
输出:输出标准逻辑向量(7到0);
r:输出标准逻辑向量(7到0)
);
端部分隔器;
行为分配器的结构是
--信号输入:无符号(7到0);
信号n:无符号(7到0);
信号商:无符号(7到0);
信号余数:无符号(7到0);
信号a:无符号(7到0);
信号b:无符号(7到0);
信号c:无符号(7到0);
信号d:无符号(7到0);
信号零:无符号(7到0);
信号一:无符号(7到0);
信号二:无符号(7到0);
信号三:无符号(7到0);
信号四:无符号(7到0);
信号x:无符号(7到0);
信号y:无符号(7到0);
信号z:无符号(7到0);
信号t:无符号(7到0);
开始
a这很容易。if语句是顺序语句,不能在适合并发语句的位置使用。它需要在此处的进程语句(并发语句)中。错误与除法无关。您可以在不丢失错误的情况下减少代码。这将使它成为一个新的主题,这个问题(及其答案)将对更多的读者有用。