Ip 为什么vivado的分布式内存块设计的ROM可以'；不行？
我试图使用vivado提供的分布式内存生成器来存储一些数据。但是ROM外的模拟总是“xxx” 以下是我的IP设置： 这是我的测试台：Ip 为什么vivado的分布式内存块设计的ROM可以'；不行？,ip,verilog,vivado,rom,Ip,Verilog,Vivado,Rom,我试图使用vivado提供的分布式内存生成器来存储一些数据。但是ROM外的模拟总是“xxx” 以下是我的IP设置： 这是我的测试台： `timescale 1ns/1ps module tb(); reg clk; reg [6:0] a; wire [11:0] out; initial begin clk <= 0; a <= 7'b0000000; end always #5 clk <= ~clk; always #20 a <= a + 1;
`timescale 1ns/1ps
module tb();
reg clk;
reg [6:0] a;
wire [11:0] out;
initial
begin
clk <= 0;
a <= 7'b0000000;
end
always #5 clk <= ~clk;
always #20 a <= a + 1;
temp u (.a(a), .clk(clk), .spo(out));
defparam u.inst.C_READ_MIF = "temp.mif";//initial ROM
endmodule
DEPTH = 160;
WIDTH = 12;
ADDRESS_RADIX = BIN;
DATA_RADIX = BIN;
CONTENT
BEGIN
0:100000000010;
1:100000000100;
10:000000000011;
11:100000000001;
100:100000001011;
101:000000000001;
110:000000000001;
111:000000000000;
1000:000000000000;
1001:100000000100;
1010:100000001000;
1011:100000000100;
1100:100000000001;
1101:100000000001;
1110:100000000000;
1111:000000000110;
10000:100000000011;
10001:100000000101;
10010:000000000000;
10011:100000000100;
10100:100000000011;
10101:000000000001;
10110:100000000000;
10111:000000000001;
11000:100000000100;
11001:000000000100;
11010:000000000000;
11011:000000000101;
11100:000000000101;
11101:000000000010;
11110:000000000011;
11111:100000000011;
100000:100000000010;
100001:000000000001;
100010:000000000001;
100011:000000000100;
100100:100000000000;
100101:000000000100;
100110:100000000000;
100111:100000000010;
101000:000000001000;
101001:000000000110;
101010:000000000000;
101011:100000000010;
101100:100000000101;
101101:100000000100;
101110:100000000011;
101111:100000001010;
110000:100000000000;
110001:100000000010;
110010:000000000111;
110011:100000000011;
110100:000000000001;
110101:100000000011;
110110:100000000100;
110111:000000000110;
111000:100000000000;
111001:100000000001;
111010:000000000100;
111011:000000000011;
111100:000000001010;
111101:100000001011;
111110:100000000000;
111111:000000000010;
1000000:000000000000;
1000001:000000000010;
1000010:000000000001;
1000011:000000000100;
1000100:100000000100;
1000101:100000000111;
1000110:000000000100;
1000111:100000000010;
1001000:000000000001;
1001001:100000000000;
1001010:000000000010;
1001011:100000000001;
1001100:100000001010;
1001101:000000000110;
1001110:100000000100;
1001111:000000000100;
1010000:100000000001;
1010001:000000000000;
1010010:000000000000;
1010011:000000000100;
1010100:000000000100;
1010101:100000000001;
1010110:100000000100;
1010111:000000000100;
1011000:100000000110;
1011001:000000000010;
1011010:000000000010;
1011011:000000000100;
1011100:000000001000;
1011101:100000000101;
1011110:100000000000;
1011111:000000000000;
1100000:000000000000;
1100001:100000000110;
1100010:100000000111;
1100011:100000000001;
1100100:100000000000;
1100101:100000000001;
1100110:100000001000;
1100111:000000000010;
1101000:000000000010;
1101001:000000000011;
1101010:100000000010;
1101011:000000000010;
1101100:100000000110;
1101101:100000000000;
1101110:000000000000;
1101111:000000000001;
1110000:000000000011;
1110001:100000000011;
1110010:100000000011;
1110011:100000000101;
1110100:000000001011;
1110101:100000000000;
1110110:100000000001;
1110111:000000000001;
1111000:000000000001;
1111001:100000000000;
1111010:100000000001;
1111011:000000001000;
1111100:000000000000;
1111101:100000000001;
1111110:100000000110;
1111111:100000000100;
10000000:000000000101;
10000001:000000000100;
10000010:000000000101;
10000011:100000000011;
10000100:100000000101;
10000101:000000000001;
10000110:000000000101;
10000111:000000000001;
10001000:000000000001;
10001001:000000000111;
10001010:100000000000;
10001011:100000000100;
10001100:100000001000;
10001101:000000000010;
10001110:100000000010;
10001111:100000000000;
10010000:000000000101;
10010001:000000000011;
10010010:100000000001;
10010011:000000000110;
10010100:000000000110;
10010101:100000000010;
10010110:100000000000;
10010111:000000000000;
10011000:100000000000;
10011001:100000000100;
10011010:000000000100;
10011011:000000000111;
10011100:000000000001;
10011101:100000000010;
10011110:100000000110;
10011111:100000000100;
END
`时间刻度为1ns/1ps
模块tb（）；
注册时钟；
reg[6:0]a；
线[11:0]输出；
最初的
开始
clk很可能是初始化失败。检查模拟日志文件中的错误消息，如“无法打开…”
我之所以怀疑，是因为Vivado中的Xilinx文件位置非常非常糟糕。它们与simulation目录相关，simulation目录可以是Vivado项目目录中的4或5个目录。不仅如此，当我切换到一个新版本时，深度最近发生了变化，我必须调整每个旧测试台上的每一条路径！（谢谢Xilinx！！）
这是一个模拟示例，我必须在我的测试台（tb）中传递文件名：
我使用的目录结构是：
---+--tb
| |
| +-- test_bench.sv
|
+--test_data
| |
| +-- testpattern_00.bin
|
+--vivado_directory
|
+--vivado_project.xpr
很可能是初始化失败。检查模拟日志文件中的错误消息，如“无法打开…”
我之所以怀疑，是因为Vivado中的Xilinx文件位置非常非常糟糕。它们与simulation目录相关，simulation目录可以是Vivado项目目录中的4或5个目录。不仅如此，当我切换到一个新版本时，深度最近发生了变化，我必须调整每个旧测试台上的每一条路径！（谢谢Xilinx！！）
这是一个模拟示例，我必须在我的测试台（tb）中传递文件名：
我使用的目录结构是：
---+--tb
| |
| +-- test_bench.sv
|
+--test_data
| |
| +-- testpattern_00.bin
|
+--vivado_directory
|
+--vivado_project.xpr
谢谢你的即时回复！我将temp.mif文件添加到simulation目录中，它确实改变了结果，即out仍然是000而不是xxx。我真的很困惑…谢谢你的即时回答！我将temp.mif文件添加到simulation目录中，它确实改变了结果，即out仍然是000而不是xxx。我真的很困惑。。。