如何在verilog中存储ram中的数据
这是一个刺激文件:如何在verilog中存储ram中的数据,verilog,Verilog,这是一个刺激文件: module final_stim; reg [7:0] in,in_data; reg clk,rst_n,rd,wr,rd_data,wr_data; wire [7:0] out,out_wr; wire[7:0] d; integer i; reg kld,f; reg [127:0]key; wire [127:0] key_expand; wire [7:0]out_data; reg [7:0] k; //wire [7:0] k1,k2,k3,k4,k5,
module final_stim;
reg [7:0] in,in_data;
reg clk,rst_n,rd,wr,rd_data,wr_data;
wire [7:0] out,out_wr;
wire[7:0] d;
integer i;
reg kld,f;
reg [127:0]key;
wire [127:0] key_expand;
wire [7:0]out_data;
reg [7:0] k;
//wire [7:0] k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16;
wire [7:0] out_data1;
**//key_expand is da output which is giving 10 streams of size 128 bits.**
assign k1=key_expand[127:120];
assign k2=key_expand[119:112];
assign k3=key_expand[111:104];
assign k4=key_expand[103:96];
assign k5=key_expand[95:88];
assign k6=key_expand[87:80];
assign k7=key_expand[79:72];
assign k8=key_expand[71:64];
assign k9=key_expand[63:56];
assign k10=key_expand[55:48];
assign k11=key_expand[47:40];
assign k12=key_expand[39:32];
assign k13=key_expand[31:24];
assign k14=key_expand[23:16];
assign k15=key_expand[15:8];
assign k16=key_expand[7:0];
**// then the module of memory is instanciated.
//here k1 is sent as input.but i don know how to save the other values of k.
//i tried to use for loop but it dint help**
memory m1(clk,rst_n,rd, wr,k1,out_data1);
aes_sbox b(out,d);
initial
begin
clk=1'b1;
rst_n=1'b0;
#20
rst_n = 1;
wr_data=1'b1;
in=8'hd4;
#20
in=8'h27;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h11;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hae;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'he0;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hbf;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h98;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hf1;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hb8;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hb4;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h5d;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'he5;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h1e;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h41;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h52;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h30;
rd_data=1'b0;
wr_data=1'b1;
#20
wr_data=1'b0;
#380
rd_data=1'b1;
#320
rd_data = 1'b0;
///////////////
#10
kld = 1'b1;
key=128'h 2b7e151628aed2a6abf7158809cf4f3c;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b0;
#10
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
wr = 1'b0;
#20
rd = 1'b1;
end
always
#10 clk=~clk;
always@(posedge clk)
begin
#10000
$stop;
end
endmodule
我在clk
的每个posedge有一个128位的位流,即每个长度为128位的总共10位流
我想把128位的流分成8,8位,并且必须将它们存储在8位宽的ram/内存中
我把8,8比特分配给8比特大小的电线。这样就有16根电线。我使用的是双端口ram。当我在刺激中调用内存模块时,我不知道如何输入,因为我有16条不同的电线,名为k1
到k16
//生成128位流的密钥扩展模块(密钥引用为流)
//该代码在时钟的每个正边缘生成10个128位的密钥
模块按键扩展(kld、clk、按键、按键扩展);
输入kld、clk;
输入[127:0]键;
导线[31:0]w0,w1,w2,w3;
输出[127:0]键\u展开;
reg[31:0]w[3:0];
导线[7:0]k1、k2、k3、k4、k5、k6、k7、k8、k9、k10、k11、k12、k13、k14、k15、k16;
导线[31:0]c0、c1、c2、c3;
导线[31:0]tmp_w;
连线[31:0]子字;
导线[31:0]rcon;
赋值w0=w[0];
赋值w1=w[1];
赋值w2=w[2];
分配w3=w[3];
始终@(posedge clk)w[0]您需要一个不同的内存块,或者一个总线多路复用器(移位寄存器),它可以将128个流序列化为16倍更高的时钟8位流
从简单实用的角度来看,我的建议是使用不同的内存块。事实上,128位寄存器似乎就足够了。请注意,您的测试只使用一个键,所以它不会检查内存的功能
但是,在您尝试修复任何东西之前,请真正清理您的代码。ouut
真的是一个好的变量名吗?请点击“101010”按钮格式化代码,并用标点正确的英语书写。我已经编辑了这篇文章。请帮忙!我已经贴出了答案。请将每个句子的第一个字母大写,不要省略单词之间的空格,也不要缩写任何内容。@potatosatter我已经发布了生成128位长度的流和刺激的代码。请检查该代码。我正在研究AES的字节收缩体系结构,可能存在重复。我需要分割128位的流。我会发送生成10个流的代码,这些流需要以8位格式存储在内存中吗?@anum:我没有看到其中的10个。10不是二进制的整数。字节脉动结构需要16个流。通过使用状态机,您可能会得到8个流。但它不会有那么高的效率。无论如何,8位内存只能是一个瓶颈。您希望尽可能快地将128位流馈送到脉动处理器,而不缩小其范围。
//Key expansion module to generate 128 bit streams(key reffered to as stream)
//This code generates 10 keys of 128 bits each at each positive edge of clock
module key_expansion(kld,clk,key,key_expand);
input kld,clk;
input [127:0] key;
wire [31:0] w0,w1,w2,w3;
output [127:0] key_expand;
reg [31:0] w[3:0];
wire [7:0] k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16;
wire [31:0] c0,c1,c2,c3;
wire [31:0] tmp_w;
wire [31:0] subword;
wire [31:0] rcon;
assign w0 = w[0];
assign w1 = w[1];
assign w2 = w[2];
assign w3 = w[3];
always @(posedge clk) w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon;
always @(posedge clk) w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon;
always @(posedge clk) w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon;
always @(posedge clk) w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon;
assign tmp_w = w[3];
aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24]));
aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16]));
aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08]));
aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00]));
aes_rcon r0( .clk(clk), .kld(kld), .out_rcon(rcon));
assign key_expand={w0,w1,w2,w3};
endmodule
//stimulus for key generation
module stim_key_exp;
reg kld ,clk;
reg [127:0]key;
wire [127:0] key_expand;
key_expansion x(kld,clk,key,key_expand);
initial
begin
clk=1'b1;
kld = 1'b1;
#20
kld=1'b0;
key=128'h 2b28ab097eaef7cf15d2154f16a6883c;
end
always
#5 clk=~clk;
always@(posedge clk)
begin
$monitor($time," key_expand=%h\n",key_expand);
#110
$stop;
end
endmodule