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Verilog 如何在vivado上使led处于低激活状态_Verilog_Xilinx_Vivado - Fatal编程技术网

Verilog 如何在vivado上使led处于低激活状态

Verilog 如何在vivado上使led处于低激活状态,verilog,xilinx,vivado,Verilog,Xilinx,Vivado,此程序表示一个有限状态机,带有计数为5的7段led。我需要让它处于低激活状态,而不是高激活状态,但我不确定如何做到这一点。我还包括测试台。我知道对时钟使用always语句会更好,但我可以稍后再处理 `timescale 1ns / 1ps //inputs, outputs module Counter( input u, input clrn, input clk, output reg a, output reg b, output reg

此程序表示一个有限状态机,带有计数为5的7段led。我需要让它处于低激活状态,而不是高激活状态,但我不确定如何做到这一点。我还包括测试台。我知道对时钟使用always语句会更好,但我可以稍后再处理

`timescale 1ns / 1ps

//inputs, outputs

module Counter(
    input u,
    input clrn,
    input clk,
    output reg a,
    output reg b,
    output reg c,
    output reg d,
    output reg e,
    output reg f,
    output reg g);

    reg [2:0] ns; //next state
    reg [2:0] q; //present state
//declaration of the states    
    parameter [2:0] S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;

    always @ (posedge clk or negedge clrn)
    begin
    if(~clrn) //if reset present state q goes to 0
        q = S0;
    else
    begin
        case(q) //tests present state
            S0:
            if (u==1) begin
                ns = S1;
                a = 1'b0;
                b = 1'b1;
                c = 1'b1;
                d = 1'b0;
                e = 1'b0;
                f = 1'b0;
                g = 1'b0;
            end
            else begin
                ns = S5;
                a = 1'b1;
                b = 1'b0;
                c = 1'b1;
                d = 1'b1;
                e = 1'b0;
                f = 1'b1;
                g = 1'b1;
            end

            S1:
            if (u==1) begin
                ns = S2;
                a = 1'b1;
                b = 1'b1;
                c = 1'b0;
                d = 1'b1;
                e = 1'b1;
                f = 1'b0;
                g = 1'b1;
            end
            else begin
                ns = S0;
                a = 1'b1;
                b = 1'b1;
                c = 1'b1;
                d = 1'b1;
                e = 1'b1;
                f = 1'b1;
                g = 1'b0;
            end

            S2:
            if (u==1) begin
                ns = S3;
                a = 1'b1;
                b = 1'b1;
                c = 1'b1;
                d = 1'b1;
                e = 1'b0;
                f = 1'b0;
                g = 1'b1;
            end
            else begin
                ns = S1;
                a = 1'b0;
                b = 1'b1;
                c = 1'b1;
                d = 1'b0;
                e = 1'b0;
                f = 1'b0;
                g = 1'b0;
            end            

            S3:
            if (u==1) begin
                ns = S4;
                a = 1'b0;
                b = 1'b1;
                c = 1'b1;
                d = 1'b0;
                e = 1'b0;
                f = 1'b1;
                g = 1'b1;
            end
            else begin
                ns = S2;
                a = 1'b1;
                b = 1'b0;
                c = 1'b1;
                d = 1'b1;
                e = 1'b0;
                f = 1'b1;
                g = 1'b1;
            end   

            S4:
            if (u==1) begin
                ns = S5;
                a = 1'b1;
                b = 1'b0;
                c = 1'b1;
                d = 1'b1;
                e = 1'b0;
                f = 1'b1;
                g = 1'b1;
            end
            else begin
                ns = S3;
                a = 1'b1;
                b = 1'b1;
                c = 1'b1;
                d = 1'b1;
                e = 1'b0;
                f = 1'b0;
                g = 1'b1;
            end

            S5:
            if (u==1) begin
                ns = S0;
                a = 1'b1;
                b = 1'b1;
                c = 1'b1;
                d = 1'b1;
                e = 1'b1;
                f = 1'b1;
                g = 1'b0;
            end
            else begin
                ns = S4;
                a = 1'b0;
                b = 1'b1;
                c = 1'b1;
                d = 1'b0;
                e = 1'b0;
                f = 1'b1;
                g = 1'b1;
            end

        endcase

        q = ns;

    end

    end

endmodule
试验台:

`timescale 1ns / 1ps

module testbench;

reg U, CLK, CLRN;
wire A, B, C, D, E, F, G;

Counter inst(

.clk (CLK),
.u (U),
.clrn (CLRN),
.a (A),
.b (B),
.c (C),
.d (D),
.e (E),
.f (F),
.g (G));

initial

begin //CLRN starts low, CLK starts high, U starts high

CLRN = 1'b0;

CLK = 1'b1;

U = 1'b1;

//CLK will change every ns

#1 CLRN = 1'b1;
CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0; //On the ns 17 u will change to low
U = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

#1 CLK = 1'b0;

#1 CLK = 1'b1;

end

endmodule

多谢各位

最快的方法是简单地更改每个状态a到g的分配

在第一个案例中,你有这个

            a = 1'b0;
            b = 1'b1;
            c = 1'b1;
            d = 1'b0;
            e = 1'b0;
            f = 1'b0;
            g = 1'b0;
将其更改为此,您将反转输出的极性

            a = 1'b1; // old setting 1'b0;
            b = 1'b0; // old setting 1'b1;
            c = 1'b0; // old setting 1'b1;
            d = 1'b1; // old setting 1'b0;
            e = 1'b1; // old setting 1'b0;
            f = 1'b1; // old setting 1'b0;
            g = 1'b1; // old setting 1'b0;
或者,您可以创建新的寄存器

reg a_n, b_n, c_n, d_n, e_n, f_n, g_n;
然后检查所有寄存器分配,并将它们更改为这些新的寄存器名称

a_n = 1'b0;
b_n = 1'b1;
c_n = 1'b1;
d_n = 1'b0;
e_n = 1'b0;
f_n = 1'b0;
g_n = 1'b0;
然后创建一个新的always块

// Invert the register outputs 
always @ (a_n or b_n or c_n or d_n or e_n or f_n or g_n)
begin
    a <= ~a_n;
    b <= ~b_n;
    c <= ~c_n;
    d <= ~d_n;
    e <= ~e_n;
    f <= ~f_n;
    g <= ~g_n;
end
//反转寄存器输出
始终@(a_n或b_n或c_n或d_n或e_n或f_n或g_n)
开始
A.