正在尝试在Verilog中实现堆栈。什么'；代码怎么了？
我是Verilog新手，所以请原谅任何新手的错误。我试图在verilog中实现一个3字节的堆栈。使用R_W读写（push/pop）和2D数组存储堆栈内容正在尝试在Verilog中实现堆栈。什么'；代码怎么了？,verilog,fpga,xilinx,hdl,Verilog,Fpga,Xilinx,Hdl,我是Verilog新手，所以请原谅任何新手的错误。我试图在verilog中实现一个3字节的堆栈。使用R_W读写（push/pop）和2D数组存储堆栈内容 `timescale 1ns / 1ps module one(R_W,PUSH,POP); input PUSH; input R_W; output POP; wire [31:0] PUSH; reg [31:0] POP; wire R_W; reg [31:0] temp[0:3]; integer tos
`timescale 1ns / 1ps
module one(R_W,PUSH,POP);
input PUSH;
input R_W;
output POP;
wire [31:0] PUSH;
reg [31:0] POP;
wire R_W;
reg [31:0] temp[0:3];
integer tos = 3;
if(R_W == 1 && tos != 3)
begin
POP = temp[tos];
end
if(R_W == 0 && tos != 0)
begin
tos = tos +1;
POP = temp[tos];
end
endmodule
`include"one.v"
module one_test();
wire pop;
reg [31:0] push;
wire r_w;
initial begin
push = 2'd12;
r_w = 0;
#10
$finish;
end
one one(r_w,push,pop);
endmodule
`timescale 1ns / 1ps
module one(R_W,PUSH,POP);
input PUSH;
input R_W;
output POP;
wire [31:0] PUSH;
reg [31:0] POP;
wire R_W;
reg [31:0] temp[0:3];
integer tos = 3;
if(R_W == 1 && tos != 3)
begin
tos = tos + 1;
POP = temp[tos];
end
if(R_W == 0 && tos != 0)
begin
tos = tos - 1;
POP = temp[tos];
end
endmodule
我不确定语法，因为我自己更喜欢VHDL。但是因为tos的逻辑有问题。我决定回答它。好的！这是正确的代码。它现在应该编译：
`timescale 1ns / 1ps
module one(clk,R_W,PUSH,POP);
input clk;
input [31:0] PUSH;
input R_W;
output [31:0] POP;
//wire [31:0] PUSH;
reg [31:0] POP;
wire R_W;
reg [31:0] temp[0:3];
integer tos = 3;
always @ (posedge clk)
if(R_W == 1 && tos != 3)
begin
POP = temp[tos];
tos = tos + 1;
end
else if(R_W == 0 && tos != 0)
begin
POP = temp[tos];
tos = tos - 1;
end
endmodule
`timescale 1ns / 1ps
module one(R_W,PUSH,POP);
input [31:0] PUSH;
input R_W;
output [31:0] POP;
//wire [31:0] PUSH;
reg [31:0] POP;
wire R_W;
reg [31:0] temp[0:3];
integer tos = 3;
always @ (R_W, tos)
if(R_W == 1 && tos != 3)
begin
POP = temp[tos];
tos = tos + 1;
end
else if(R_W == 0 && tos != 0)
begin
POP = temp[tos];
tos = tos - 1;
end
endmodule
感谢Renato的代码更正，但我已经改进了代码并使用了推送功能。以下是Verilog中的代码和测试台： 模块：
`timescale 1ns / 1ps
module some(clk,R_W,PUSH,POP);
input clk;
input [31:0] PUSH;
input R_W;
output [31:0] POP;
wire [31:0] PUSH;
reg [31:0] POP;
wire R_W;
reg [31:0] temp[0:3];
integer tos = 3;
always @ (posedge clk)
if(R_W == 1 && tos != 3)
begin
POP = temp[tos];
tos = tos + 1;
end
else if(R_W == 0 && tos != 0)
begin
temp[tos] = PUSH;
tos = tos - 1;
end
endmodule
module some_test();
reg clk;
reg r_w;
integer push;
wire [31:0] pop;
always begin
#1 clk = !clk;
end
initial begin
clk = 0;
#1 r_w = 0;
#1 push = 'd9;
#10
$finish;
end
some some(clk,r_w,push,pop);
endmodule
你的问题是什么？请签出。您缺少一个
始终错误