Verilog 错误记录。ABC阶段的自由文件读取
我正在使用一个liberty文件，它已经在不同的合成工具上测试过了。它工作正常。但是当我尝试在这里使用它时，下面显示了一个错误 流程步骤如下：Verilog 错误记录。ABC阶段的自由文件读取,verilog,yosys,Verilog,Yosys,我正在使用一个liberty文件，它已经在不同的合成工具上测试过了。它工作正常。但是当我尝试在这里使用它时，下面显示了一个错误 流程步骤如下： [leela@ins108 exp]$ yosys /----------------------------------------------------------------------------\ |
[leela@ins108 exp]$ yosys
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2015 Clifford Wolf <clifford@clifford.at> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.5 (git sha1 UNKNOWN, clang 3.4.2 -fPIC -Os)
yosys> read_verilog top.v submod1.v submod2.v bottom2.v
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `top.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend.
Parsing Verilog input from `submod1.v' to AST representation.
Generating RTLIL representation for module `\submod1'.
Successfully finished Verilog frontend.
3. Executing Verilog-2005 frontend.
Parsing Verilog input from `submod2.v' to AST representation.
Generating RTLIL representation for module `\submod2'.
Successfully finished Verilog frontend.
4. Executing Verilog-2005 frontend.
Parsing Verilog input from `bottom2.v' to AST representation.
Generating RTLIL representation for module `\bottom2'.
Successfully finished Verilog frontend.
yosys> hierarchy -check -top top
5. Executing HIERARCHY pass (managing design hierarchy).
Top module: \top
Used module: \submod2
Used module: \bottom2
Used module: \submod1
Removed 0 unused modules.
Mapping positional arguments of cell submod2.bottom2i (bottom2).
yosys> proc
6. Executing PROC pass (convert processes to netlists).
6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
6.3. Executing PROC_INIT pass (extract init attributes).
6.4. Executing PROC_ARST pass (detect async resets in processes).
6.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\bottom2.$proc$bottom2.v:15$7'.
creating decoder for signal `$0\areg[6:0]'.
creating decoder for signal `$0\breg[6:0]'.
Creating decoders for process `\submod2.$proc$submod2.v:13$5'.
creating decoder for signal `$0\creg[3:0]'.
Creating decoders for process `\submod1.$proc$submod1.v:9$2'.
creating decoder for signal `$0\do[6:0]'.
Creating decoders for process `\top.$proc$top.v:14$1'.
creating decoder for signal `$0\ireg[4:0]'.
6.6. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\bottom2.\areg' using process `\bottom2.$proc$bottom2.v:15$7'.
created $dff cell `$procdff$36' with positive edge clock.
Creating register for signal `\bottom2.\breg' using process `\bottom2.$proc$bottom2.v:15$7'.
created $dff cell `$procdff$37' with positive edge clock.
Creating register for signal `\submod2.\creg' using process `\submod2.$proc$submod2.v:13$5'.
created $dff cell `$procdff$38' with positive edge clock.
Creating register for signal `\submod1.\do' using process `\submod1.$proc$submod1.v:9$2'.
created $dff cell `$procdff$39' with positive edge clock.
Creating register for signal `\top.\ireg' using process `\top.$proc$top.v:14$1'.
created $dff cell `$procdff$40' with positive edge clock.
6.7. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 4 empty switches in `\bottom2.$proc$bottom2.v:15$7'.
Removing empty process `bottom2.$proc$bottom2.v:15$7'.
Removing empty process `submod2.$proc$submod2.v:13$5'.
Removing empty process `submod1.$proc$submod1.v:9$2'.
Removing empty process `top.$proc$top.v:14$1'.
Cleaned up 4 empty switches.
yosys> opt
7. Executing OPT pass (performing simple optimizations).
7.1. Executing OPT_CONST pass (perform const folding).
7.2. Executing OPT_SHARE pass (detect identical cells).
Finding identical cells in module `\bottom2'.
Finding identical cells in module `\submod2'.
Finding identical cells in module `\submod1'.
Finding identical cells in module `\top'.
Removed a total of 0 cells.
7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizier on module \bottom2..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Root of a mux tree: $procmux$34 (pure)
Root of a mux tree: $procmux$22 (pure)
Root of a mux tree: $ternary$bottom2.v:13$6 (pure)
Analyzing evaluation results.
Running muxtree optimizier on module \submod2..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Root of a mux tree: $ternary$submod2.v:9$4 (pure)
Analyzing evaluation results.
Running muxtree optimizier on module \submod1..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Root of a mux tree: $ternary$submod1.v:10$3 (pure)
Analyzing evaluation results.
Running muxtree optimizier on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \bottom2.
Optimizing cells in module \submod2.
Optimizing cells in module \submod1.
Optimizing cells in module \top.
Performed a total of 0 changes.
7.5. Executing OPT_SHARE pass (detect identical cells).
Finding identical cells in module `\bottom2'.
Finding identical cells in module `\submod2'.
Finding identical cells in module `\submod1'.
Finding identical cells in module `\top'.
Removed a total of 0 cells.
7.6. Executing OPT_RMDFF pass (remove dff with constant values).
Replaced 0 DFF cells.
7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \bottom2..
Finding unused cells or wires in module \submod2..
Finding unused cells or wires in module \submod1..
Finding unused cells or wires in module \top..
7.8. Executing OPT_CONST pass (perform const folding).
7.9. Finished OPT passes. (There is nothing left to do.)
yosys> techmap
8. Executing TECHMAP pass (map to technology primitives).
8.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `<techmap.v>' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
Mapping top.$procdff$40 ($dff) with simplemap.
Mapping submod1.$ternary$submod1.v:10$3 ($mux) with simplemap.
Mapping submod1.$procdff$39 ($dff) with simplemap.
Mapping submod2.$ternary$submod2.v:9$4 ($mux) with simplemap.
Mapping submod2.$procdff$38 ($dff) with simplemap.
Mapping bottom2.$procmux$13 ($mux) with simplemap.
Mapping bottom2.$ternary$bottom2.v:13$6 ($mux) with simplemap.
Mapping bottom2.$eq$bottom2.v:17$8 ($eq) with simplemap.
Mapping bottom2.$eq$bottom2.v:22$9 ($eq) with simplemap.
Mapping bottom2.$eq$bottom2.v:27$10 ($eq) with simplemap.
Mapping bottom2.$eq$bottom2.v:32$11 ($eq) with simplemap.
Mapping bottom2.$procmux$16 ($mux) with simplemap.
Mapping bottom2.$procmux$19 ($mux) with simplemap.
Mapping bottom2.$procmux$22 ($mux) with simplemap.
Mapping bottom2.$procmux$25 ($mux) with simplemap.
Mapping bottom2.$procmux$28 ($mux) with simplemap.
Mapping bottom2.$procmux$31 ($mux) with simplemap.
Mapping bottom2.$procmux$34 ($mux) with simplemap.
Mapping bottom2.$procdff$36 ($dff) with simplemap.
Mapping bottom2.$procdff$37 ($dff) with simplemap.
No more expansions possible.
yosys> dfflibmap -liberty scadv12atk_cmos10sf_hvt_ss_0p9v_125c.lib
9. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
final dff cell mappings:
unmapped dff cell: $_DFF_N_
unmapped dff cell: $_DFF_P_
unmapped dff cell: $_DFF_NN0_
unmapped dff cell: $_DFF_NN1_
unmapped dff cell: $_DFF_NP0_
unmapped dff cell: $_DFF_NP1_
unmapped dff cell: $_DFF_PN0_
unmapped dff cell: $_DFF_PN1_
unmapped dff cell: $_DFF_PP0_
unmapped dff cell: $_DFF_PP1_
unmapped dff cell: $_DFFSR_NNN_
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
unmapped dff cell: $_DFFSR_PNN_
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
Mapping DFF cells in module `\bottom2':
Mapping DFF cells in module `\submod2':
Mapping DFF cells in module `\submod1':
Mapping DFF cells in module `\top':
yosys> abc -liberty scadv12atk_cmos10sf_hvt_ss_0p9v_125c.lib
10. Executing ABC pass (technology mapping using ABC).
10.1. Extracting gate netlist of module `\bottom2' to `<abc-temp-dir>/input.blif'..
Extracted 79 gates and 105 wires to a netlist network with 24 inputs and 21 outputs.
10.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lib -w /home/leela/synth/exp/scadv12atk_cmos10sf_hvt_ss_0p9v_125c.lib
ABC: Reading SCL library from file "/home/leela/synth/exp/scadv12atk_cmos10sf_hvt_ss_0p9v_125c.lib" has failed.
ABC: ** cmd error: aborting 'source <abc-temp-dir>/abc.script'
ABC: File "/home/leela/synth/exp/scadv12atk_cmos10sf_hvt_ss_0p9v_125c.lib". Line 64611. Failed to parse entry "".
ABC: Parsing failed. Parsing time = 0.10 sec
ABC: Table cannot be found
ABC: Memory = 4.80 MB. Time = 0.15 sec
ERROR: Can't open ABC output file `/tmp/yosys-abc-6GrNPU/output.blif'.
[leela@ins108exp]$yosys
/----------------------------------------------------------------------------\
| |
|yosys——yosys开放合成套件|
| |
|版权所有（C）2012-2015 Clifford Wolf|
| |
|为任何目的使用、复制、修改和/或分发本软件的权限|
|特此授予目的，无论是否收费，前提是|
|版权声明和本许可声明出现在所有副本中|
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|本软件按“原样”提供，作者不承担任何担保责任|
|关于本软件，包括对以下内容的所有默示保证：|
|适销性和适合性。在任何情况下，提交人均不对以下行为负责：|
|任何特殊、直接、间接或后果性损害或任何损害|
|因使用、数据或利润损失而导致的任何损失，无论是在|
|因以下原因引起的合同诉讼、疏忽或其他侵权诉讼：|
|或与本软件的使用或性能有关|
| |
\----------------------------------------------------------------------------/
Yosys 0.5（git sha1未知，clang 3.4.2-fPIC-Os）
yosys>read_verilog top.v submod1.v submod2.v bottom2.v
1.正在执行Verilog-2005前端。
正在将Verilog输入从'top.v'解析为AST表示。
正在为模块“\top”生成RTLIL表示。
已成功完成Verilog前端。
2.正在执行Verilog-2005前端。
正在将Verilog输入从'submod1.v'解析为AST表示。
正在为模块“\submod1”生成RTLIL表示。
已成功完成Verilog前端。
3.正在执行Verilog-2005前端。
正在将Verilog输入从'submod2.v'解析为AST表示。
正在为模块“\submod2”生成RTLIL表示。
已成功完成Verilog前端。
4.正在执行Verilog-2005前端。
正在将Verilog输入从'bottom2.v'解析为AST表示。
正在为模块“\bottom2”生成RTLIL表示。
已成功完成Verilog前端。
yosys>层次结构-选中-顶部
5.执行层次结构传递（管理设计层次结构）。
顶部模块：\Top
已使用的模块：\submod2
已使用的模块：\2
已使用的模块：\submod1
已删除0个未使用的模块。
映射单元格submod2.bottom2i（bottom2）的位置参数。
yosys>proc
6.执行PROC pass（将进程转换为网络列表）。
6.1. 执行PROC_CLEAN pass（从决策树中删除空开关）。
清理了0个空开关。
6.2. 执行PROC_RMDEAD pass（从决策树中删除死分支）。
共移除了0例死亡病例。
6.3. 执行PROC_INIT pass（提取INIT属性）。
6.4. 执行PROC_ARST pass（检测进程中的异步重置）。
6.5. 执行PROC_MUX pass（将决策树转换为多路复用器）。
正在为进程“\bottom2.$proc$bottom2.v:15$7”创建解码器。
正在为信号“$0\areg[6:0]”创建解码器。
正在为信号“$0\breg[6:0]”创建解码器。
正在为进程“\submod2.$proc$submod2.v:13$5”创建解码器。
正在为信号“$0\creg[3:0]”创建解码器。
正在为进程“\submod1.$proc$submod1.v:9$2”创建解码器。
正在为信号“$0\do[6:0]”创建解码器。
正在为进程“\top.$proc$top.v:14$1”创建解码器。
正在为信号“$0\ireg[4:0]”创建解码器。
6.6. 执行PROC_DFF pass（将进程同步转换为FFs）。
正在使用进程“\bottom2.$proc$bottom2.v:15$7”为信号“\bottom2.\areg”创建寄存器。
创建了带正边缘时钟的$dff单元“$procdff$36”。
正在使用进程“\bottom2.$proc$bottom2.v:15$7”为信号“\bottom2.\breg”创建寄存器。
创建了带正边缘时钟的$dff单元“$procdff$37”。
正在使用进程“\submod2.$proc$submod2.v:13$5”为信号“\submod2.\creg”创建寄存器。
创建了带正边缘时钟的$dff单元“$procdff$38”。
正在使用进程“\submod1.$proc$submod1.v:9$2”为信号“\submod1.\do”创建寄存器。
创建了带正边缘时钟的$dff单元“$procdff$39”。
正在使用进程“\top.$proc$top.v:14$1”为信号“\top.\ireg”创建寄存器。
创建了带正边缘时钟的$dff单元“$procdff$40”。
6.7. 执行PROC_CLEAN pass（从决策树中删除空开关）。
在“\bottom2.$proc$bottom2.v:15$7”中找到并清理了4个空开关。
删除空进程'bottom2.$proc$bottom2.v:15$7'。
正在删除空进程'submod2.$proc$submod2.v:13$5'。
正在删除空进程'submod1.$proc$submod1.v:9$2'。
正在删除空进程'top.$proc$top.v:14$1'。
清理了4个空开关。
yosys>opt
7.执行OPT pass（执行简单的优化）。
7.1. 执行OPT_CONST pass（执行CONST折叠）。
7.2. 执行OPT_共享传递（检测相同的单元格）。
在模块“%2”中找到相同的单元格。
在模块“\submod2”中找到相同的单元格。
在模块“\submod1”中找到相同的单元格。
在模块“\top”中找到相同的单元格。
总共删除了0个单元格。
7.3. 执行OPT_MUXTREE pass（检测mux树中的死分支）。
正在模块上运行muxtree optimizier\bottom2。。
创建mux树的内部表示。
评估mux树的内部表示。
mux树的根：$procmux$34（纯）
mux树的根：$procmux$22（纯）
mux树的根：$Trialum$bottom2.v:13$6（纯）
分析评估结果。
正在模块\submod2.上运行muxtree optimizier。。
创建mux树的内部表示。
评估mux树的内部表示。
ABC: Reading SCL library from file "/home/leela/synth/exp/scadv12atk_cmos10sf_hvt_ss_0p9v_125c.lib" has failed.
ABC: ** cmd error: aborting 'source <abc-temp-dir>/abc.script'
ABC: File "/home/leela/synth/exp/scadv12atk_cmos10sf_hvt_ss_0p9v_125c.lib". Line 64611. Failed to parse entry "".
ABC: Parsing failed. Parsing time = 0.10 sec