Can';t适合计数器Verilog中的可设置性
我已经写了向上/向下计数器,并为可设置的起点创建了代码。到目前为止还不错,但我想不出如何把它加到柜台上。我必须强调的是,我对Verilog和类似的语言是完全陌生的Can';t适合计数器Verilog中的可设置性,verilog,counter,updown,Verilog,Counter,Updown,我已经写了向上/向下计数器,并为可设置的起点创建了代码。到目前为止还不错,但我想不出如何把它加到柜台上。我必须强调的是,我对Verilog和类似的语言是完全陌生的 //UTILS reg [2:0] delay; wire clock; reg[3:0] tens; reg[3:0] units; wire[5:0] number; reg[13:0] shift; integer i; //ASSIGNS assign number[5:0] = SW[5:0]; a
//UTILS
reg [2:0] delay;
wire clock;
reg[3:0] tens;
reg[3:0] units;
wire[5:0] number;
reg[13:0] shift;
integer i;
//ASSIGNS
assign number[5:0] = SW[5:0];
assign up = SW[7];
assign start = SW[6];
//PRESCALER
always@ (posedge MCLK)
begin
delay <= delay + 1;
end
assign clock = &delay;
//MAIN COUNTER
always@ (posedge clock)
begin
if (start)
begin
if (up) //going up
begin
if (units == 4'd3 && tens == 4'd6)
begin //63 reached
units <= 0;
tens <=0;
end
if (units==4'd9)
begin //x9 reached
units <= 0;
tens <= tens + 1;
end
else
units <= units + 1; //typical case
end
else //goin down
begin
if (units == 4'd0)
if ( tens ==4'd0) //00 reached back to 63
begin
units <= 4'd3;
tens <= 4'd6;
end
else
begin //x0 reached
tens <= tens-1;
units <= 4'd9;
end
else
begin //typical case
units <= units -1;
end
end
end
end //MAIN COUNTER END
您正在使用派生时钟来控制主计数器。相反,使用主时钟
MCLK
,并将delay
的逻辑用作条件语句
由于您希望在更改number
时存储新值,因此您需要存储上一个number
值并进行比较
根据您的描述,您的代码应该如下所示:
//MAIN COUNTER
always@ (posedge MCLK)
begin
if (start && &delay)
begin
/* your up/down logic here */
end
else if (number != prev_number)
begin // Clear previous number and store new number
prev_number <= number;
units <= new_units;
tens <= new_tens;
end
end
// Calculate new units and tens from number
always @* begin
shift[13:6] = 0;
shift[5:0] = number;
//BINARY TO BCD
for (i=0; i<6; i=i+1) begin
if (shift[9:6] >= 5)
shift[9:6] = shift[9:6] + 3;
if (shift[13:10] >= 5)
shift[13:10] = shift[13:10] + 3;
shift = shift << 1;
end
new_units = shift[9:6];
new_tens = shift[13:10];
end
//主计数器
始终@(posedge MCLK)
开始
如果(启动和延迟)
开始
/*你的上/下逻辑在这里*/
结束
else if(编号!=上一个编号)
开始//清除以前的号码并存储新号码
上一个号码
dek7seg ss1(
.bits(units[3:0]),
.seg(DISP1[6:0])
);
dek7seg ss10(
.bits(tens[3:0]),
.seg(DISP2[6:0])
);
endmodule
//MAIN COUNTER
always@ (posedge MCLK)
begin
if (start && &delay)
begin
/* your up/down logic here */
end
else if (number != prev_number)
begin // Clear previous number and store new number
prev_number <= number;
units <= new_units;
tens <= new_tens;
end
end
// Calculate new units and tens from number
always @* begin
shift[13:6] = 0;
shift[5:0] = number;
//BINARY TO BCD
for (i=0; i<6; i=i+1) begin
if (shift[9:6] >= 5)
shift[9:6] = shift[9:6] + 3;
if (shift[13:10] >= 5)
shift[13:10] = shift[13:10] + 3;
shift = shift << 1;
end
new_units = shift[9:6];
new_tens = shift[13:10];
end