Verilog 为什么我会得到一个推断闩锁错误？
我正在尝试使用FSM在系统Verilog中创建自动售货机，在合成过程中，软件警告我此错误： [Synth 8-327]推断变量锁存器 “FSM_sequential_statoProssimo_reg”[“macchinetamerendine.sv”：87] 代码是：Verilog 为什么我会得到一个推断闩锁错误？,verilog,system-verilog,hdl,vivado,Verilog,System Verilog,Hdl,Vivado,我正在尝试使用FSM在系统Verilog中创建自动售货机，在合成过程中，软件警告我此错误： [Synth 8-327]推断变量锁存器 “FSM_sequential_statoProssimo_reg”[“macchinetamerendine.sv”：87] 代码是： ... module FSM_50_Cent ( input logic Clk100_MHz, Reset, input logic Cent20, Cent50, Euro1, Confirm, in
...
module FSM_50_Cent (
input logic Clk100_MHz, Reset,
input logic Cent20, Cent50, Euro1, Confirm,
input logic [7:0] Switch50,
output logic Er, r10, r20, r40, r50
);
enum logic [4:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9,
S10, S11, S12, S13, S14, S15, S16, S17} Stati; //STATES
logic [4:0] Stato, statoProssimo; //STATE AND NEXTSTATE
always_ff @(posedge Clk100_MHz, posedge Reset) //FLIP FLOP
begin
if(Reset) Stato <= S0;
else Stato <= statoProssimo;
end
always_comb //NEXT STATE LOGIC
begin
if((|Switch50) == 1)
begin
case(Stato)
S0: if (Cent20) statoProssimo = S1;
else if (Cent50) statoProssimo = S3;
else if (Euro1) statoProssimo = S8;
else if (Confirm) statoProssimo = S0;
S1: if (Cent20) statoProssimo = S2;
else if (Cent50) statoProssimo = S5;
else if (Euro1) statoProssimo = S9;
else if (Confirm) statoProssimo = S1;
S2: if (Cent20) statoProssimo = S4;
else if (Cent50) statoProssimo = S7;
else if (Euro1) statoProssimo = S10;
else if (Confirm) statoProssimo = S2;
S3: if (Confirm) statoProssimo = S0;
S4: if (Confirm) statoProssimo = S0;
S5: if (Confirm) statoProssimo = S0;
S6: if (Confirm) statoProssimo = S0;
S7: if (Confirm) statoProssimo = S0;
S8: if (Confirm) statoProssimo = S0;
S9: if (Confirm) statoProssimo = S0;
S10: if (Confirm) statoProssimo = S0;
default statoProssimo = S0;
endcase
end
end
...
endmodule
...
。。。
模块FSM_50_分(
输入逻辑Clk100_MHz，复位，
输入逻辑Cent20，Cent50，Euro1，确认，
输入逻辑[7:0]开关50，
输出逻辑Er、r10、r20、r40、r50
);
枚举逻辑[4:0]{S0，S1，S2，S3，S4，S5，S6，S7，S8，S9，
S10、S11、S12、S13、S14、S15、S16、S17}Stati//州
逻辑[4:0]Stato，statoProssimo//州和下一州
始终_ff@（posedge Clk100 _MHz，posedge重置）//触发器
开始
如果（重置）Stato以避免闩锁，则在所有条件下，始终梳
块必须为statoProssimo
分配一个值
但是，例如，当Switch50
为0时，块不会将值分配给statoProssimo
。因此，Verilog模拟将保留statoProssimo
的值。这就推断出一个内存元素（闩锁）
您可以添加一个else
子句并赋值。例如：
always_comb //NEXT STATE LOGIC
begin
if((|Switch50) == 1)
begin
case(Stato)
...
endcase
end
else statoProssimo = S0;
end
这同样适用于每个案例
项目。您应该使用else
子句来赋值
S0: if (Cent20) statoProssimo = S1;
else if (Cent50) statoProssimo = S3;
else if (Euro1) statoProssimo = S8;
else statoProssimo = S0;
您需要决定在每种情况下分配什么值。浏览工具对答案的解释，并查看此代码的始终\u comb
部分
module FSM_50_Cent (
input logic Clk100_MHz, Reset,
input logic Cent20, Cent50, Euro1, Confirm,
input logic [7:0] Switch50,
output logic Er, r10, r20, r40, r50
);
typedef enum logic [4:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9,
S10, S11, S12, S13, S14, S15, S16, S17} Stati; //STATES
Stati Stato, statoProssimo; //STATE AND NEXTSTATE
//STATE FLIP FLOPS
always_ff @(posedge Clk100_MHz, posedge Reset)
if(Reset) Stato <= S0;
else Stato <= statoProssimo;
//NEXT STATE LOGIC
always_comb begin
statoProssimo = Stato;
if((|Switch50) == 1)
case(Stato)
S0: if (Cent20) statoProssimo = S1;
else if (Cent50) statoProssimo = S3;
else if (Euro1) statoProssimo = S8;
else if (Confirm) statoProssimo = S0;
S1: if (Cent20) statoProssimo = S2;
else if (Cent50) statoProssimo = S5;
else if (Euro1) statoProssimo = S9;
else if (Confirm) statoProssimo = S1;
S2: if (Cent20) statoProssimo = S4;
else if (Cent50) statoProssimo = S7;
else if (Euro1) statoProssimo = S10;
else if (Confirm) statoProssimo = S2;
S3,S4,
S5,S6,
S7,S8,
S9,S10: if (Confirm) statoProssimo = S0;
default statoProssimo = S0;
endcase
end
模块FSM\u 50(
输入逻辑Clk100_MHz，复位，
输入逻辑Cent20，Cent50，Euro1，确认，
输入逻辑[7:0]开关50，
输出逻辑Er、r10、r20、r40、r50
);
typedef枚举逻辑[4:0]{S0、S1、S2、S3、S4、S5、S6、S7、S8、S9，
S10、S11、S12、S13、S14、S15、S16、S17}Stati//州
Stati Stato、statoProssimo//州和下一州
//状态触发器
始终_ff@（posedge Clk100_MHz，posedge重置）
如果（重置）Stato