Vhdl 计算Altera设计的fmax
在Quartus上完成设计编译后，我得到了fmax的多个结果，如下所示。我想知道，这意味着什么？如何计算所有设计的fmax 我的设计是实现以下等式：Vhdl 计算Altera设计的fmax,vhdl,fpga,state-machine,intel-fpga,quartus,Vhdl,Fpga,State Machine,Intel Fpga,Quartus,在Quartus上完成设计编译后，我得到了fmax的多个结果，如下所示。我想知道，这意味着什么？如何计算所有设计的fmax 我的设计是实现以下等式： for(i = 1; i < 5; i++) { T += ( ((Rv[i] - Ru[i]))^2 + ((Iv[i] - Iu[i]))^2 ) } （i=1；i
for(i = 1; i < 5; i++)
{
T += ( ((Rv[i] - Ru[i]))^2 + ((Iv[i] - Iu[i]))^2 )
}
{
T+=（（Rv[i]-Ru[i]）^2+（（Iv[i]-Iu[i]））^2）
}
-平方器是9位。
-T是21位 这是我设计的FSM 根据以上，这是我的代码
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity EDCfunction_TopEntity is
port
(
clk, reset : in std_logic;
Rv1 : in std_logic_vector (8-1 downto 0);
Iv1 : in std_logic_vector (8-1 downto 0);
Ru1 : in std_logic_vector (8-1 downto 0);
Iu1 : in std_logic_vector (8-1 downto 0);
Rv2 : in std_logic_vector (8-1 downto 0);
Iv2 : in std_logic_vector (8-1 downto 0);
Ru2 : in std_logic_vector (8-1 downto 0);
Iu2 : in std_logic_vector (8-1 downto 0);
Rv3 : in std_logic_vector (8-1 downto 0);
Iv3 : in std_logic_vector (8-1 downto 0);
Ru3 : in std_logic_vector (8-1 downto 0);
Iu3 : in std_logic_vector (8-1 downto 0);
Rv4 : in std_logic_vector (8-1 downto 0);
Iv4 : in std_logic_vector (8-1 downto 0);
Ru4 : in std_logic_vector (8-1 downto 0);
Iu4 : in std_logic_vector (8-1 downto 0);
T : out std_logic_vector (21-1 downto 0)
);
end EDCfunction_TopEntity;
architecture behavioral of EDCfunction_TopEntity is
type clock_state is (zero, zero_clk2, one, two, two_clk2, three, three_clk2, four, four_clk2, five, six, seven, eight);
type add_sub_type is array (4-1 downto 0) of std_logic_vector (21-1 downto 0);
type squarer_in_type is array (2-1 downto 0) of std_logic_vector (9-1 downto 0);
type squarer_out_type is array (2-1 downto 0) of std_logic_vector (18-1 downto 0);
signal cc_state, cn_state : clock_state;
signal clk_reg_file, reset_reg_file, s_wr_en : std_logic;
signal add_sub_flage, state_mux : std_logic_vector (4-1 downto 0);
signal dataa_add_sub, datab_add_sub, result_add_sub : add_sub_type;
signal dataa_squarer : squarer_in_type;
signal result_squarer : squarer_out_type;
signal w_addr_reg_file, r_addr_reg_file : std_logic_vector (8-1 downto 0);
signal s_w_data_0, s_w_data_1, s_w_data_2, s_w_data_3, s_w_data_4, s_w_data_5, s_w_data_6, s_w_data_7,
s_r_data_0, s_r_data_1, s_r_data_2, s_r_data_3, s_r_data_4, s_r_data_5, s_r_data_6, s_r_data_7
: std_logic_vector (21-1 downto 0);
alias R0 is s_w_data_0(21-1 downto 0);
alias R0H is s_w_data_0(21-1 downto 10);
alias R0L is s_w_data_0(9 downto 0);
alias R1 is s_w_data_1(21-1 downto 0);
alias R1H is s_w_data_1(21-1 downto 10);
alias R1L is s_w_data_1(9 downto 0);
alias R2 is s_w_data_2(21-1 downto 0);
alias R2H is s_w_data_2(21-1 downto 10);
alias R2L is s_w_data_2(9 downto 0);
alias R3 is s_w_data_3(21-1 downto 0);
alias R3H is s_w_data_3(21-1 downto 10);
alias R3L is s_w_data_3(9 downto 0);
alias R4 is s_w_data_4(21-1 downto 0);
alias R4H is s_w_data_4(21-1 downto 10);
alias R4L is s_w_data_4(9 downto 0);
alias R5 is s_w_data_5(21-1 downto 0);
alias R5H is s_w_data_5(21-1 downto 10);
alias R5L is s_w_data_5(9 downto 0);
alias R6 is s_w_data_6(21-1 downto 0);
alias R6H is s_w_data_6(21-1 downto 10);
alias R6L is s_w_data_6(9 downto 0);
alias R7 is s_w_data_7(21-1 downto 0);
alias R7H is s_w_data_7(21-1 downto 10);
alias R7L is s_w_data_7(9 downto 0);
component lpm_adder_subtractor
port
(
add_sub : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (20 DOWNTO 0)
);
end component;
component lpm_squarer
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
end component;
component register_file
port
(
clk, reset : in std_logic;
wr_en : in std_logic;
w_addr : in std_logic_vector (8-1 downto 0);
w_data_0 : in std_logic_vector (21-1 downto 0);
w_data_1 : in std_logic_vector (21-1 downto 0);
w_data_2 : in std_logic_vector (21-1 downto 0);
w_data_3 : in std_logic_vector (21-1 downto 0);
w_data_4 : in std_logic_vector (21-1 downto 0);
w_data_5 : in std_logic_vector (21-1 downto 0);
w_data_6 : in std_logic_vector (21-1 downto 0);
w_data_7 : in std_logic_vector (21-1 downto 0);
r_addr : in std_logic_vector (8-1 downto 0);
r_data_0 : out std_logic_vector (21-1 downto 0);
r_data_1 : out std_logic_vector (21-1 downto 0);
r_data_2 : out std_logic_vector (21-1 downto 0);
r_data_3 : out std_logic_vector (21-1 downto 0);
r_data_4 : out std_logic_vector (21-1 downto 0);
r_data_5 : out std_logic_vector (21-1 downto 0);
r_data_6 : out std_logic_vector (21-1 downto 0);
r_data_7 : out std_logic_vector (21-1 downto 0)
);
end component;
begin
A0 : lpm_adder_subtractor port map (add_sub_flage(0), dataa_add_sub(0), datab_add_sub(0), result_add_sub(0));
A1 : lpm_adder_subtractor port map (add_sub_flage(1), dataa_add_sub(1), datab_add_sub(1), result_add_sub(1));
A2 : lpm_adder_subtractor port map (add_sub_flage(2), dataa_add_sub(2), datab_add_sub(2), result_add_sub(2));
A3 : lpm_adder_subtractor port map (add_sub_flage(3), dataa_add_sub(3), datab_add_sub(3), result_add_sub(3));
S0 : lpm_squarer port map (dataa_squarer(0), result_squarer(0));
S1 : lpm_squarer port map (dataa_squarer(1), result_squarer(1));
U0 : register_file port map (clk, reset_reg_file, s_wr_en, w_addr_reg_file, s_w_data_0, s_w_data_1, s_w_data_2,
s_w_data_3, s_w_data_4, s_w_data_5, s_w_data_6, s_w_data_7, r_addr_reg_file,
s_r_data_0, s_r_data_1, s_r_data_2, s_r_data_3, s_r_data_4, s_r_data_5, s_r_data_6,
s_r_data_7);
process (cc_state, reset, Rv1, Iv1, Ru1, Iu1, Rv2, Iv2, Ru2, Iu2, Rv3, Iv3, Ru3, Iu3, Rv4, Iv4, Ru4, Iu4)
begin
case cc_state is
when zero =>
s_wr_en <= '1';
w_addr_reg_file <= "11111111";
R0H <= std_logic_vector(resize(signed(Rv1), R0H'length));
R0L <= std_logic_vector(resize(signed(Ru1), R0L'length));
R1H <= std_logic_vector(resize(signed(Iv1), R1H'length));
R1L <= std_logic_vector(resize(signed(Iu1), R1L'length));
R2H <= std_logic_vector(resize(signed(Rv2), R2H'length));
R2L <= std_logic_vector(resize(signed(Ru2), R2L'length));
R3H <= std_logic_vector(resize(signed(Iv2), R3H'length));
R3L <= std_logic_vector(resize(signed(Iu2), R3L'length));
R4H <= std_logic_vector(resize(signed(Rv3), R4H'length));
R4L <= std_logic_vector(resize(signed(Ru3), R4L'length));
R5H <= std_logic_vector(resize(signed(Iv3), R5H'length));
R5L <= std_logic_vector(resize(signed(Iu3), R5L'length));
R6H <= std_logic_vector(resize(signed(Rv4), R6H'length));
R6L <= std_logic_vector(resize(signed(Ru4), R6L'length));
R7H <= std_logic_vector(resize(signed(Iv4), R7H'length));
R7L <= std_logic_vector(resize(signed(Iu4), R7L'length));
--clk_reg_file <= '1';
--T <= result_add_sub(0);
cn_state <= zero_clk2;
when zero_clk2 =>
r_addr_reg_file <= "11111111";
cn_state <= one;
when one =>
s_wr_en <= '0';
--w_addr_reg_file <= "00001111";
add_sub_flage(0) <= '0';
add_sub_flage(1) <= '0';
add_sub_flage(2) <= '0';
add_sub_flage(3) <= '0';
--r_addr_reg_file <= "00001111";
dataa_add_sub(0) <= std_logic_vector(resize(signed(s_r_data_0 (21-1 downto 10)), dataa_add_sub(0)'length));
datab_add_sub(0) <= std_logic_vector(resize(signed(s_r_data_0 (9 downto 0)), dataa_add_sub(0)'length));
--s_w_data_0 <= result_add_sub(0);
--w_addr_reg_file <= "00000001";
dataa_add_sub(1) <= std_logic_vector(resize(signed(s_r_data_1 (21-1 downto 10)), dataa_add_sub(1)'length));
datab_add_sub(1) <= std_logic_vector(resize(signed(s_r_data_1 (9 downto 0)), dataa_add_sub(1)'length));
--s_w_data_1 <= result_add_sub(1);
--w_addr_reg_file <= "00000010";
dataa_add_sub(2) <= std_logic_vector(resize(signed(s_r_data_2 (21-1 downto 10)), dataa_add_sub(2)'length));
datab_add_sub(2) <= std_logic_vector(resize(signed(s_r_data_2 (9 downto 0)), dataa_add_sub(2)'length));
--s_w_data_2 <= result_add_sub(2);
--w_addr_reg_file <= "00000100";
dataa_add_sub(3) <= std_logic_vector(resize(signed(s_r_data_3 (21-1 downto 10)), dataa_add_sub(3)'length));
datab_add_sub(3) <= std_logic_vector(resize(signed(s_r_data_3 (9 downto 0)), dataa_add_sub(3)'length));
--s_w_data_3 <= result_add_sub(3);
--w_addr_reg_file <= "00001000";
--T <= result_add_sub(3);
--clk_reg_file <= '1';
--r_addr_reg_file <= "11110000";
cn_state <= two;
--state_mux <= "0001";
when two =>
s_wr_en <= '1';
w_addr_reg_file <= "00001111";
R0 <= result_add_sub(0);
R1 <= result_add_sub(1);
R2 <= result_add_sub(2);
R3 <= result_add_sub(3);
dataa_squarer(0) <= result_add_sub(0) (9-1 downto 0);
dataa_squarer(1) <= result_add_sub(1) (9-1 downto 0);
dataa_add_sub(0) <= std_logic_vector(resize(signed(s_r_data_4 (21-1 downto 10)), dataa_add_sub(0)'length));
datab_add_sub(0) <= std_logic_vector(resize(signed(s_r_data_4 (9 downto 0)), dataa_add_sub(0)'length));
dataa_add_sub(1) <= std_logic_vector(resize(signed(s_r_data_5 (21-1 downto 10)), dataa_add_sub(1)'length));
datab_add_sub(1) <= std_logic_vector(resize(signed(s_r_data_5 (9 downto 0)), dataa_add_sub(1)'length));
dataa_add_sub(2) <= std_logic_vector(resize(signed(s_r_data_6 (21-1 downto 10)), dataa_add_sub(2)'length));
datab_add_sub(2) <= std_logic_vector(resize(signed(s_r_data_6 (9 downto 0)), dataa_add_sub(2)'length));
dataa_add_sub(3) <= std_logic_vector(resize(signed(s_r_data_7 (21-1 downto 10)), dataa_add_sub(3)'length));
datab_add_sub(3) <= std_logic_vector(resize(signed(s_r_data_7 (9 downto 0)), dataa_add_sub(3)'length));
cn_state <= two_clk2;
when two_clk2 =>
cn_state <= three;
when three =>
--s_wr_en <= '1';
w_addr_reg_file <= "11110011";
R0 <= std_logic_vector(resize(signed(result_squarer(0)), R0'length));
R1 <= std_logic_vector(resize(signed(result_squarer(1)), R0'length));
R4 <= result_add_sub(0);
R5 <= result_add_sub(1);
R6 <= result_add_sub(2);
R7 <= result_add_sub(3);
add_sub_flage(0) <= '1';
dataa_add_sub(0) <= std_logic_vector(resize(signed(result_squarer(0)), dataa_add_sub(0)'length));
datab_add_sub(0) <= std_logic_vector(resize(signed(result_squarer(1)), datab_add_sub(0)'length));
dataa_squarer(0) <= s_r_data_2 (9-1 downto 0);
dataa_squarer(1) <= s_r_data_3 (9-1 downto 0);
cn_state <= three_clk2;
when three_clk2 =>
cn_state <= four;
when four =>
w_addr_reg_file <= "00000110";
R0 <= result_add_sub(0);
R1 <= std_logic_vector(resize(signed(result_squarer(0)), R0'length));
R2 <= std_logic_vector(resize(signed(result_squarer(1)), R0'length));
add_sub_flage(1) <= '1';
dataa_add_sub(1) <= std_logic_vector(resize(signed(result_squarer(0)), dataa_add_sub(1)'length));
datab_add_sub(1) <= std_logic_vector(resize(signed(result_squarer(1)), datab_add_sub(1)'length));
dataa_squarer(0) <= s_r_data_4 (9-1 downto 0);
dataa_squarer(1) <= s_r_data_5 (9-1 downto 0);
cn_state <= four_clk2;
when four_clk2 =>
cn_state <= five;
when five =>
w_addr_reg_file <= "00001110";
R1 <= result_add_sub(1);
R2 <= std_logic_vector(resize(signed(result_squarer(0)), R2'length));
R3 <= std_logic_vector(resize(signed(result_squarer(1)), R3'length));
add_sub_flage(2) <= '1';
dataa_add_sub(0) <= R0;
datab_add_sub(0) <= result_add_sub(1);
dataa_add_sub(2) <= std_logic_vector(resize(signed(result_squarer(0)), dataa_add_sub(2)'length));
datab_add_sub(2) <= std_logic_vector(resize(signed(result_squarer(1)), datab_add_sub(2)'length));
dataa_squarer(0) <= s_r_data_6 (9-1 downto 0);
dataa_squarer(1) <= s_r_data_7 (9-1 downto 0);
cn_state <= six;
when six =>
w_addr_reg_file <= "00001111";
R0 <= result_add_sub(0);
R1 <= result_add_sub(2);
R2 <= std_logic_vector(resize(signed(result_squarer(0)), R2'length));
R3 <= std_logic_vector(resize(signed(result_squarer(1)), R3'length));
add_sub_flage(3) <= '1';
dataa_add_sub(0) <= result_add_sub(0);
datab_add_sub(0) <= result_add_sub(2);
dataa_add_sub(3) <= std_logic_vector(resize(signed(result_squarer(0)), dataa_add_sub(2)'length));
datab_add_sub(3) <= std_logic_vector(resize(signed(result_squarer(1)), datab_add_sub(2)'length));
cn_state <= seven;
when seven =>
w_addr_reg_file <= "00000011";
R0 <= result_add_sub(0);
R1 <= result_add_sub(3);
dataa_add_sub(0) <= result_add_sub(0);
datab_add_sub(0) <= result_add_sub(3);
--R0 <= result_add_sub(0);
--T <= result_add_sub(0);
cn_state <= eight;
when eight =>
w_addr_reg_file <= "00000001";
R0 <= result_add_sub(0);
T <= result_add_sub(0);
cn_state <= zero;
end case;
--if(state_mux = "0001") then
--end if;
end process;
process (clk, reset)
begin
reset_reg_file <= reset;
if(reset = '1') then
cc_state <= zero;
elsif (clk'event and clk = '1') then
cc_state <= cn_state;
end if;
end process;
end behavioral;
ieee库；
使用ieee.std_logic_1164.all；
使用ieee.numeric_std.all；
实体EDCfunction\u TopEntity为
港口
(
时钟，复位：在标准逻辑中；
Rv1:std_逻辑_向量中（8-1向下至0）；
Iv1：标准逻辑向量（8-1向下至0）；
Ru1:std_逻辑_向量中（8-1向下至0）；
Iu1：标准逻辑向量（8-1向下至0）；
Rv2：在标准逻辑向量中（8-1向下至0）；
Iv2：标准逻辑向量（8-1向下至0）；
Ru2:std_逻辑_向量中（8-1向下至0）；
Iu2：标准逻辑向量（8-1向下至0）；
Rv3:std_逻辑_向量中（8-1向下至0）；
Iv3：标准逻辑向量（8-1向下至0）；
Ru3:std_逻辑_向量中（8-1向下至0）；
Iu3：标准逻辑向量（8-1向下至0）；
Rv4:std_逻辑_向量中（8-1向下至0）；
Iv4：标准逻辑向量（8-1向下至0）；
Ru4:std_逻辑_向量中（8-1向下至0）；
Iu4：标准逻辑向量（8-1向下至0）；
T:out标准逻辑向量（21-1向下至0）
);
结束EDCfunction_TopEntity；
EDCfunction\u TopEntity的架构行为是
类型时钟状态为（零、零、二、二、三、三、四、四、五、六、七、八）；
类型add_sub_类型是标准逻辑_向量（21-1向下到0）的数组（4-1向下到0）；
_type中的类型squarer_是标准_逻辑_向量（9-1向下到0）的数组（2-1向下到0）；
类型squarer_out_type是标准逻辑_向量（18-1向下到0）的数组（2-1向下到0）；
信号cc_状态、cn_状态：时钟_状态；
信号clk_reg_文件、reset_reg_文件、s_wr_en:std_逻辑；
信号叠加，状态复用：标准逻辑向量（4-1到0）；
信号数据A\u添加\u子、数据添加\u子、结果添加\u子：添加\u子类型；
信号数据a_squarer:squarer_in_类型；
信号结果平方器：平方器输出类型；
信号w_addr_reg_文件，r_addr_reg_文件：标准逻辑向量（8-1向下至0）；
信号s_w_数据0、s_w_数据1、s_w_数据2、s_w_数据3、s_w_数据4、s_w_数据5、s_w_数据6、s_w_数据7、，
s_r_数据0、s_r_数据1、s_r_数据2、s_r_数据3、s_r_数据4、s_r_数据5、s_r_数据6、s_r_数据7
：标准逻辑向量（21-1向下至0）；
别名R0是s_w_数据_0（21-1向下到0）；
别名R0H为s_w_数据_0（21-1向下至10）；
别名R0L是s_w_数据_0（9到0）；
别名R1是s_w_数据_1（21-1向下至0）；
别名R1H是s_w_数据_1（21-1到10）；
别名R1L是s_w_数据_1（9到0）；
别名R2是s_w_数据_2（21-1到0）；
别名R2H是s_w_数据_2（21-1到10）；
别名R2L是s_w_数据_2（9到0）；
别名R3是s_w_数据_3（21-1向下到0）；
别名R3H为s_w_数据_3（21-1至10）；
别名R3L是s_w_数据_3（9到0）；
别名R4是s_w_数据_4（21-1向下到0）；
别名R4H为s_w_数据_4（21-1向下至10）；
别名R4L是s_w_数据_4（9到0）；
别名R5是s_w_数据_5（21-1向下到0）；
别名R5H是s_w_数据_5（21-1到10）；
别名R5L是s_w_数据_5（9到0）；
别名R6是s_w_数据_6（21-1向下到0）；
别名R6H是s_w_数据_6（21-1到10）；
别名R6L是s_w_数据_6（9到0）；
别名R7是s_w_数据_7（21-1向下到0）；
别名R7H是s_w_数据_7（21-1到10）；
别名R7L是s_w_数据_7（9到0）；
分量lpm_加法器_减法器
港口
(
在STD_逻辑中添加_sub:；
数据A：标准逻辑向量（20到0）；
数据：标准逻辑向量（20到0）；
结果：输出标准逻辑向量（20到0）
);
端部元件；
分量lpm_平方器
港口
(
数据A：标准逻辑向量（8到0）；
结果：输出标准逻辑向量（17到0）
);
端部元件；
组件寄存器文件
港口
(
时钟，复位：在标准逻辑中；
wr_en：标准逻辑中；
w_addr:in标准逻辑向量（8-1向下至0）；
w_data_0：标准逻辑向量（21-1向下至0）；
w_数据_1：标准逻辑_向量（21-1向下至0）；
w_数据_2：标准逻辑_向量（21-1向下至0）；
w_数据_3：标准逻辑_向量（21-1向下至0）；
w_数据_4：标准逻辑_向量（21-1向下至0）；
w_数据_5：标准逻辑向量（21-1向下至0）；
w_数据_6：标准逻辑_向量（21-1向下至0）；
w_数据_7：标准逻辑向量（21-1向下至0）；
r_addr:in标准逻辑向量（8-1向下至0）；
r_数据_0：输出标准逻辑_向量（21-1向下至0）；
r_数据_1：输出标准逻辑_向量（21-1向下至0）；
r_数据_2：输出标准逻辑_向量（21-1向下至0）；
r_数据_3：输出标准逻辑_向量（21-1向下至0）；
r_数据_4：输出标准逻辑_向量（21-1向下至0）；
r_数据_5：输出标准逻辑_向量（21-1向下至0）；
r_数据_6：输出标准逻辑_向量（21-1向下至0）；
r_数据_7：输出标准逻辑_向量（21-1向下至0）
);
端部元件；
开始
A0:lpm_加法器_减法器端口映射（加法（0）、数据加法（0）、数据加法（0）、结果加法（0））；
A1:lpm_加法器_减法器端口映射（加法（1）、数据加法（1）、数据加法（1）、结果加法（1））；
A2:lpm_加法器_减法器端口映射（加法（2）、数据加法（2）、数据加法（2）、结果加法（2））；
A3:lpm_加法器_减法器端口映射（加法（3）、数据加法（3）、数据加法（3）、结果加法（3））；
S0:lpm_squar