VHDL输入输出端口设置为高阻抗

更新

我更新了测试台代码，但现在，似乎databuffer没有驱动信号

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY databus_buffer_tb IS
END databus_buffer_tb;


ARCHITECTURE dataflow OF databus_buffer_tb IS
  SIGNAL T_Idata:STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL T_Odata:STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL T_Ctrl:STD_LOGIC:='0';
  COMPONENT databus_buffer IS
      PORT
         (
           --IDATA represent the bus lines that comes from the uC for reading and writing;
           --ODATA represents the bus lines that communicate with the internal bus;
           IDATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
           CTRL:     IN      STD_LOGIC;
           ODATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000"
     );
   END COMPONENT;

BEGIN
  databuffer:databus_buffer PORT MAP
    (
      IDATA=>T_Idata,
      CTRL=>T_Ctrl,
      ODATA=>T_Odata
      );
  PROCESS
  BEGIN



    T_Idata<="00001111";

    T_Ctrl<='0';
    WAIT FOR 10 ns;
    assert(T_Odata="00001111") REPORT "Expected 00001111" SEVERITY error;

    T_Odata<="11110000";

    T_Ctrl<='1';
    WAIT FOR 10 ns;
    assert(T_Idata="11110000") REPORT "Expected 11110000" SEVERITY error;


    T_Ctrl<='Z';
    WAIT FOR 10 ns;
    assert(T_Idata="ZZZZZZZZ") REPORT "Expected Z FOR T_Idata" SEVERITY error;
    assert(T_Odata="ZZZZZZZZ") REPORT "Expected Z FOR T_Odata" SEVERITY error;
    wait;
  END PROCESS;
END dataflow;

ieee库；
使用ieee.std_logic_1164.all；
实体数据总线缓冲区是
结束数据总线\缓冲区\ tb；
databus_buffer_tb的体系结构数据流为
信号T_Idata:STD_逻辑_向量（7到0）；
信号T_Odata:STD_逻辑向量（7到0）；
信号T_Ctrl:STD_逻辑：='0'；
组件数据总线缓冲区为
港口
(
--IDATA表示来自uC的用于读写的公交线路；
--ODATA表示与内部总线通信的总线线路；
IDATA:INOUT标准逻辑向量（7到0）：=“00000000”；
CTRL：在标准逻辑中；
ODATA:INOUT标准逻辑向量（7到0）：=“00000000”
);
端部元件；
开始
databuffer:databus\u缓冲区端口映射
(
IDATA=>T_IDATA，
CTRL=>T\U CTRL，
ODATA=>T_ODATA
);
过程
开始
T_IdataT_Ctrl，
ODATA=>T_ODATA
);
过程
开始
T_-Idata对于
T_-Idata
和
T_-ODATA
，您有多个驱动程序。这些信号由测试台和数据缓冲器驱动。最终结果由std_逻辑的分辨率函数决定。在最后一种（非工作）情况下，测试台本身将
T_-IDATA
和
T_-ODATA
驱动至低位

让我们看一个有效的案例：（示例取自原始测试台，此案例在更新的测试台中被破坏，因为信号
T_ODATA
没有初始化。）

以获得预期的结果

编辑2：必须将这些行添加到更新的测试台，否则将使用测试台以前的分配进行解析。
@23ars请注意，数据缓冲区内的
CTRL\u Z='Z'
检查不能在实际硬件中生成。在您的示例anway中不需要它，因为您在两种
else
情况下（对于每个输出信号）都指定了相同的值<代码>ODATA@23ars更新后的测试台必须在最后一个测试用例中将
T_IData
和
T_OData
驱动到所有
z
，以获得预期结果。否则，测试台以前的作业仍然有效，并用于资源配置。非常感谢您的帮助！
    library ieee;
use ieee.std_logic_1164.all;
----------------------------
-- Databus Buffer
----------------------------
ENTITY databus_buffer IS
-- data bus buffer have the next ports:
-- IDATA:        8 bit bus       ->inout
-- CTRL:        1 bit control   ->in
-- ODATA:       8 bit bus       ->inout
    PORT
    (
        --IDATA represent the bus lines that comes from the uC for reading and writing;
        --ODATA represents the bus lines that communicate with the internal bus;
            IDATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
            CTRL:     IN      STD_LOGIC;
            ODATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0)
        );



END databus_buffer;
ARCHITECTURE behaviour OF databus_buffer IS
-- behaviour of databus buffer;

BEGIN
-- is a 3 state bidirection 8 bit buffer.
-- if CTRL is 1, IDATA=ODATA; reading from counter operation
-- if CTRL is 0, ODATA=IDATA; writing to control word
-- if CTRL is Z, IDATA=Z; this happens when nor read and write are active but
-- cs is active;
-- also, data bus can be in 3rd state if the chip is not selected, this means
-- that CTRL will be Z;


    ODATA<=IDATA WHEN CTRL='0' else "ZZZZZZZZ" WHEN CTRL='Z' else (OTHERS=>'Z');
    IDATA<=ODATA WHEN CTRL='1' else "ZZZZZZZZ" WHEN CTRL='Z' else (OTHERS=>'Z');



END behaviour;  

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY databus_buffer_tb IS
END databus_buffer_tb;


ARCHITECTURE dataflow OF databus_buffer_tb IS
  SIGNAL T_Idata:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
  SIGNAL T_Odata:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
  SIGNAL T_Ctrl:STD_LOGIC:='0';
  COMPONENT databus_buffer IS
      PORT
         (
           --IDATA represent the bus lines that comes from the uC for reading and writing;
           --ODATA represents the bus lines that communicate with the internal bus;
           IDATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
           CTRL:     IN      STD_LOGIC;
           ODATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0)
     );
   END COMPONENT;

BEGIN
  databuffer:databus_buffer PORT MAP
    (
      IDATA=>T_Idata,
      CTRL=>T_Ctrl,
      ODATA=>T_Odata
      );
  PROCESS
  BEGIN
    T_Idata<="00000000";
    T_Odata<="00000000";
    T_Ctrl<='0';

    T_Idata<="00001111";
    T_ODATA<="ZZZZZZZZ";
    T_Ctrl<='0';
    WAIT FOR 10 ns;
    assert(T_Odata="00001111") REPORT "Expected 00001111" SEVERITY error;

    T_Odata<="11110000";
    T_IDATA<="ZZZZZZZZ";
    T_Ctrl<='1';
    WAIT FOR 10 ns;
    assert(T_Idata="11110000") REPORT "Expected 11110000" SEVERITY error;

    T_IData<="00000000";
    T_OData<="00000000";    
    T_Ctrl<='Z';
    WAIT FOR 10 ns;
    assert(T_Idata="ZZZZZZZZ") REPORT "Expected Z FOR T_Idata" SEVERITY error;
    assert(T_Odata="ZZZZZZZZ") REPORT "Expected Z FOR T_Odata" SEVERITY error;
    wait;
  END PROCESS;
END dataflow;

T_Idata<="00001111";
T_ODATA<="ZZZZZZZZ";
T_Ctrl<='0';
WAIT FOR 10 ns;
assert(T_Odata="00001111") REPORT "Expected 00001111" SEVERITY error;

T_IData<="00000000";
T_OData<="00000000";    
T_Ctrl<='Z';
WAIT FOR 10 ns;
assert(T_Idata="ZZZZZZZZ") REPORT "Expected Z FOR T_Idata" SEVERITY error;
assert(T_Odata="ZZZZZZZZ") REPORT "Expected Z FOR T_Odata" SEVERITY error;

T_IData<="ZZZZZZZZ";
T_OData<="ZZZZZZZZ";