32x8寄存器文件VHDL测试台
我已经用vhdl写了这个电路的汇编代码。我想用一个试验台来模拟它32x8寄存器文件VHDL测试台,vhdl,Vhdl,我已经用vhdl写了这个电路的汇编代码。我想用一个试验台来模拟它 RegWrite:1位输入(时钟) 写入寄存器编号:3位输入(写入地址) 写入数据:32位输入(数据输入)读取 寄存器编号A:3位输入(读取地址) 读取寄存器编号B:3位输入(读取地址) 端口A:32位输出(数据输出) 端口B:32位输出(数据输出) 我想我的问题是我不明白这个电路是做什么的。我选择了随机值分配给输入,但它没有输出任何东西。该电路的最佳输入是什么 以下是我的测试台文件供参考: library ieee; u
- RegWrite:1位输入(时钟)
- 写入寄存器编号:3位输入(写入地址)
- 写入数据:32位输入(数据输入)读取
- 寄存器编号A:3位输入(读取地址)
- 读取寄存器编号B:3位输入(读取地址)
- 端口A:32位输出(数据输出)
- 端口B:32位输出(数据输出)
library ieee;
use ieee.std_logic_1164.all;
entity Reg_TB is -- entity declaration
end Reg_TB;
architecture TB of Reg_TB is
component RegisterFile_32x8
port ( RegWrite: in std_logic;
WriteRegNum: in std_logic_vector(2 downto 0);
WriteData: in std_logic_vector(31 downto 0);
ReadRegNumA: in std_logic_vector(2 downto 0);
ReadRegNumB: in std_logic_vector(2 downto 0);
PortA: out std_logic_vector(31 downto 0);
PortB: out std_logic_vector(31 downto 0)
);
end component;
signal T_RegWrite : std_logic;
signal T_WriteRegNum: std_logic_vector(2 downto 0);
signal T_WriteData: std_logic_vector(31 downto 0);
signal T_ReadRegNumA: std_logic_vector(2 downto 0);
signal T_ReadRegNumB: std_logic_vector(2 downto 0);
signal T_PortA : std_logic_vector(31 downto 0);
signal T_PortB : std_logic_vector(31 downto 0);
begin
T_WriteRegNum <= "011";
T_WriteData <= "00000000000000000000000000000001";
T_ReadRegNumA <= "001";
T_ReadRegNumB <= "100";
U_RegFile: RegisterFile_32x8 port map
(T_RegWrite, T_WriteRegNum, T_WriteData,T_ReadRegNumA, T_ReadRegNumB, T_PortA, T_PortB);
-- concurrent process to offer clock signal
process
begin
T_RegWrite <= '0';
wait for 5 ns;
T_RegWrite <= '1';
wait for 5 ns;
end process;
process
begin
wait for 12 ns;
-- case 2
wait for 28 ns;
-- case 3
wait for 2 ns;
-- case 4
wait for 10 ns;
-- case 5
wait for 20 ns;
wait;
end process;
end TB;
ieee库;
使用ieee.std_logic_1164.all;
实体Reg_TB是——实体声明
终末期结核;
Reg_TB的架构TB是
组件注册表文件_32x8
端口(RegWrite:在标准逻辑中;
WriteRegNum:标准逻辑向量(2到0);
写入数据:在标准逻辑向量中(31到0);
ReadRegNumA:标准逻辑向量(2到0);
ReadRegNumB:标准逻辑向量(2到0);
端口:输出标准逻辑向量(31到0);
端口B:输出标准逻辑向量(31到0)
);
端部元件;
信号T_RegWrite:标准逻辑;
信号T_WriteRegNum:标准逻辑向量(2到0);
信号T_写入数据:标准逻辑向量(31向下至0);
信号T_ReadRegNumA:std_逻辑向量(2到0);
信号T_ReadRegNumB:std_逻辑_向量(2到0);
信号端口:标准逻辑向量(31到0);
信号T_端口B:标准逻辑向量(31向下至0);
开始
T_WriteRegNum通常,在写入地址之前读取地址不会产生任何有用的结果
您的框图显示了一个32位宽的8字深度寄存器文件,其中有两个读取端口和一个写入端口,其中RegWrite用作时钟,由写入地址的解码进行选通。稳定的WriteRegNum值和RegWrite上的上升沿会影响对WriteRegNum指定的地址的写入
两个读取端口看起来完全独立。在相应的ReadRegNumA或ReadRegNumB上指定地址应将该寄存器的内容输出到相应的输出端口
要获得有用的信息,必须首先写入该位置,否则它将是默认值((others=>'U'),与您的波形类似
在期望从某个位置读取有效数据之前,尝试写入该位置。使用可通过寄存器位置区分的值。理论上,相对于RegWrite的上升沿,应该在WriteRegNum上保留设置和保持时间
产生刺激输出的示例:
ieee库;
使用ieee.std_logic_1164.all;
使用ieee.numeric_std.all;
实体注册表文件_32x8为
港口(
RegWrite:在标准逻辑中;
WriteRegNum:标准逻辑向量(2到0);
写入数据:在标准逻辑向量中(31到0);
ReadRegNumA:标准逻辑向量(2到0);
ReadRegNumB:标准逻辑向量(2到0);
端口:输出标准逻辑向量(31到0);
端口B:输出标准逻辑向量(31到0)
);
终端实体;
注册表文件_32x8的体系结构fum为
reg_类型数组是std_逻辑_向量(31到0)的数组(0到7);
信号寄存器文件:寄存器阵列;
开始
进程(RegWrite)
开始
如果上升沿(RegWrite),则
注册表文件(到整数(无符号(WriteRegNum)))WriteRegNum,
WriteData=>WriteData,
ReadRegNumA=>ReadRegNumA,
ReadRegNumB=>ReadRegNumB,
PortA=>PortA,
PortB=>PortB
);
刺激:
过程
开始
等待20纳秒;
RegWrite有一个波形显示,您无法读取其上的信号名称,这并没有特别大的帮助。请注意,你无法区分ReadRegNumA和ReadRegNumB。与其厌恶地放弃,也许你可以更清楚地了解你不了解的内容?我在Webby Experts上发现了您的几个适用问题,这些问题表明我们可能没有以观众了解的方式阐明您不理解的内容。当您说“先写到那个位置”时,您能给我一个代码示例吗?你是说我需要先给ReadRegNumA,ReadRegNumA赋值吗?不。一个名为Read的信号与写入无关。在读取寄存器之前,必须先写入一些有意义的值。写操作需要选择一个具有WriteRegNum的位置,并在RegWrite上生成0到1的转换。通过使用ReadRegNumA或ReadRegNumB选择要读取的寄存器,即可在任一输出端口上进行读取。写入端口和读取端口是独立的。从波形中,您反复写入x“00000001”以注册三个(WriteRegNum=“011”)。第一次写入后,将ReadRegNumA或ReadRegNumB更改为“011”,该值应显示在相应的读取端口上。寄存器文件的思想是存储操作可能需要的值。双读端口寄存器文件允许读取两个不同的寄存器,并将其值用作操作数,例如作为加法器的输入。一般来说,不写入寄存器时,RegWrite可以保持高位。将其调低然后调回高位会导致写入。@JimLewis-如果您要检查问题的编辑历史记录,您会发现VHDL实现就是为了这个,而问题只标记为VHDL,没有提到实现。
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity registerfile_32x8 is
port (
RegWrite: in std_logic;
WriteRegNum: in std_logic_vector (2 downto 0);
WriteData: in std_logic_vector (31 downto 0);
ReadRegNumA: in std_logic_vector (2 downto 0);
ReadRegNumB: in std_logic_vector (2 downto 0);
PortA: out std_logic_vector (31 downto 0);
PortB: out std_logic_vector (31 downto 0)
);
end entity;
architecture fum of registerfile_32x8 is
type reg_array is array (0 to 7) of std_logic_vector(31 downto 0);
signal reg_file: reg_array;
begin
process(RegWrite)
begin
if rising_edge(RegWrite) then
reg_file(to_integer(unsigned(WriteRegNum))) <= WriteData;
end if;
end process;
PortA <= reg_file(to_integer(unsigned(ReadRegNumA)));
PortB <= reg_file(to_integer(unsigned(ReadRegNumB)));
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity reg_tb is
end entity;
architecture fum of reg_tb is
component registerfile_32x8
port (
RegWrite: in std_logic;
WriteRegNum: in std_logic_vector (2 downto 0);
WriteData: in std_logic_vector (31 downto 0);
ReadRegNumA: in std_logic_vector (2 downto 0);
ReadRegNumB: in std_logic_vector (2 downto 0);
PortA: out std_logic_vector (31 downto 0);
PortB: out std_logic_vector (31 downto 0)
);
end component;
signal RegWrite: std_logic := '1';
signal WriteRegNum: std_logic_vector (2 downto 0) := "000";
signal WriteData: std_logic_vector (31 downto 0) := (others => '0');
signal ReadRegNumA: std_logic_vector (2 downto 0) := "000";
signal ReadRegNumB: std_logic_vector (2 downto 0) := "000";
signal PortA: std_logic_vector (31 downto 0);
signal PortB: std_logic_vector (31 downto 0);
begin
DUT:
registerfile_32x8
port map (
RegWrite => RegWrite,
WriteRegNum => WriteRegNum,
WriteData => WriteData,
ReadRegNumA => ReadRegNumA,
ReadRegNumB => ReadRegNumB,
PortA => PortA,
PortB => PortB
);
STIMULUS:
process
begin
wait for 20 ns;
RegWrite <= '0';
wait for 20 ns;
RegWrite <= '1';
wait for 20 ns;
WriteData <= x"feedface";
WriteRegnum <= "001";
RegWrite <= '0';
wait for 20 ns;
RegWrite <= '1';
ReadRegNumA <= "001";
wait for 20 ns;
WriteData <= x"deadbeef";
WriteRegNum <= "010";
ReadRegNumB <= "010";
RegWrite <= '0';
wait for 20 ns;
RegWrite <= '1';
wait for 20 ns;
wait for 20 ns;
wait;
end process;
end architecture;