用于纠错的VHDL汉明码
请帮助我检查此代码,以便使用VHDL中的汉明码更正错误。我有能力发现错误,但不能纠正它。 我有三个模块:编码器、解码器和错误注入器。我感觉我的解码器有问题。下面是我的解码器代码用于纠错的VHDL汉明码,vhdl,hamming-code,Vhdl,Hamming Code,请帮助我检查此代码,以便使用VHDL中的汉明码更正错误。我有能力发现错误,但不能纠正它。 我有三个模块:编码器、解码器和错误注入器。我感觉我的解码器有问题。下面是我的解码器代码 library ieee; use ieee.std_logic_1164.all; entity hamdec8 is port( datain: in std_logic_vector (7 downto 0); parin : in std_logic_vector(4 d
library ieee;
use ieee.std_logic_1164.all;
entity hamdec8 is
port(
datain: in std_logic_vector (7 downto 0);
parin : in std_logic_vector(4 downto 0);
Dataout : out std_logic_vector(7 downto 0);
Parout : out std_logic_vector(4 downto 0);
NE : out std_logic;
DED : out std_logic;
SEC : out std_logic
);
Constant MaskP1 : std_logic_vector(7 downto 0) := "01011011";
Constant MaskP2 : std_logic_vector(7 downto 0) := "01101101";
Constant MaskP3 : std_logic_vector(7 downto 0) := "10001110";
Constant MaskP4 : std_logic_vector(7 downto 0) := "11110000";
end hamdec8;
architecture beh of hamdec8 is
signal synd : std_logic_vector(4 downto 1);
signal P0 : std_logic;
signal din1, din2, din3, din4 : std_logic_vector(7 downto 0); --to hold datain AND maskp
begin
process(Datain, Parin)
begin
NE <= '1';
DED <= '0';
SEC <= '0';
Dataout <= Datain;
Parout <= Parin;
P0 <= (Parin(0) XOR Parin(1) XOR Parin(2) XOR Parin(3) XOR
Parin(4) XOR Datain(0) XOR Datain(1) XOR Datain(2) XOR
Datain(3) XOR Datain(4) XOR Datain(5) XOR Datain(6) XOR
Datain(7));
din1 <= Datain AND MaskP1;
Synd(1) <= din1(0) XOR din1(1) XOR din1(2) XOR din1(3) XOR
din1(4) XOR din1(5) XOR din1(6) XOR din1(7) XOR Parin(1);
din2 <= Datain AND MaskP2;
Synd(2) <= din2(0) XOR din2(1) XOR din2(2) XOR din2(3) XOR
din2(4) XOR din2(5) XOR din2(6) XOR din2(7) XOR Parin(2);
din3 <= Datain AND MaskP3;
Synd(3) <= din3(0) XOR din3(1) XOR din3(2) XOR din3(3) XOR
din3(4) XOR din3(5) XOR din3(6) XOR din3(7) XOR Parin(3);
din4 <= Datain AND MaskP4;
Synd(4) <= din4(0) XOR din4(1) XOR din4(2) XOR din4(3) XOR
din4(4) XOR din4(5) XOR din4(6) XOR din4(7) XOR Parin(4);
if (synd = "0000") then
IF (P0 = '0') then
--Dataout <= Datain;
--NE <= '1';
--DED <= '0';
--SEC <= '0';
--Parout <= Parin;
null;
elsif (P0 = '1') then --single error
NE <= '0';
DED <= '0';
SEC <= '1';
case synd is
when "0000" => Parout(0) <= NOT Parin(0);
when "0001" => Parout(1) <= NOT Parin(1);
when "0010" => Parout(2) <= NOT Parin(2);
when "0011" => Dataout(0) <= NOT Datain(0);
when "0100" => Parout(3) <= NOT parin(3);
when "0101" => Dataout(1) <= NOT Datain(1);
when "0110" => Dataout(2) <= NOT Datain(2);
when "0111" => Dataout(3) <= NOT Datain(3);
when "1000" => parout(4) <= parin(4);
when "1001" => Dataout(4) <= NOT Datain(4);
when "1010" => Dataout(5) <= NOT Datain(5);
when "1011" => Dataout(6) <= NOT Datain(6);
when "1100" => Dataout(7) <= NOT Datain(7);
when others =>
Parout <= parin;
Dataout <= Datain;
end case;
Dataout <= "00000000";
Parout <= "00000";
end if;
elsif (P0 = '0') then
if (synd /= "0000") then
NE <= '0';
DED <= '1';
SEC <= '0';
Dataout <= "00000000";
Parout <= "00000";
end if;
end if;
end process;
end beh;
ieee库;
使用ieee.std_logic_1164.all;
实体hamdec8是
港口(
数据输入:标准逻辑向量(7到0);
parin:标准逻辑向量(4到0);
数据输出:输出标准逻辑向量(7到0);
输出:输出标准逻辑向量(4到0);
NE:输出标准逻辑;
DED:输出标准逻辑;
第二节:输出标准逻辑
);
常数MaskP1:std_逻辑_向量(7到0):=“01011011”;
常数MaskP2:std_逻辑_向量(7到0):=“01101101”;
常数MaskP3:std_逻辑_向量(7到0):=“10001110”;
常数MaskP4:std_逻辑_向量(7到0):=“11110000”;
第8章结束;
汉德街8号的建筑是
信号synd:std_逻辑_向量(4到1);
信号P0:std_逻辑;
信号din1、din2、din3、din4:std_逻辑_向量(7到0)--保存数据和maskp
开始
过程(数据输入,Parin)
开始
NE只有当综合征为“0000”
且总体奇偶校验为'1'
时,才会达到案例陈述中实施的校正逻辑。这还不包括所有其他可能的综合征值。单个错误elsif
的缩进使这一点令人困惑。您需要重新编写嵌套的if
语句,以便对所有综合征进行校正。您的信号P0
,synd
,din1
,din2
,din3
,din4
应该在过程中声明为变量,或者您应该从过程中提取异或计算
第二个变量,具有提取的xor计算、扩展的灵敏度列表和固定的代码缩进:
library ieee;
use ieee.std_logic_1164.all;
entity hamdec8 is
port (
datain: in std_logic_vector (7 downto 0);
parin : in std_logic_vector(4 downto 0);
Dataout : out std_logic_vector(7 downto 0);
Parout : out std_logic_vector(4 downto 0);
NE : out std_logic;
DED : out std_logic;
SEC : out std_logic
);
end hamdec8;
architecture beh of hamdec8 is
Constant MaskP1 : std_logic_vector(7 downto 0) := "01011011";
Constant MaskP2 : std_logic_vector(7 downto 0) := "01101101";
Constant MaskP3 : std_logic_vector(7 downto 0) := "10001110";
Constant MaskP4 : std_logic_vector(7 downto 0) := "11110000";
signal synd : std_logic_vector(4 downto 1);
signal P0 : std_logic;
signal din1, din2, din3, din4 : std_logic_vector(7 downto 0); --to hold datain AND maskp
begin
P0 <= Parin(0) XOR Parin(1) XOR Parin(2) XOR Parin(3) XOR Parin(4) XOR
Datain(0) XOR Datain(1) XOR Datain(2) XOR Datain(3) XOR Datain(4) XOR
Datain(5) XOR Datain(6) XOR Datain(7);
din1 <= Datain AND MaskP1;
din2 <= Datain AND MaskP2;
din3 <= Datain AND MaskP3;
din4 <= Datain AND MaskP4;
Synd(1) <= din1(0) XOR din1(1) XOR din1(2) XOR din1(3) XOR
din1(4) XOR din1(5) XOR din1(6) XOR din1(7) XOR Parin(1);
Synd(2) <= din2(0) XOR din2(1) XOR din2(2) XOR din2(3) XOR
din2(4) XOR din2(5) XOR din2(6) XOR din2(7) XOR Parin(2);
Synd(3) <= din3(0) XOR din3(1) XOR din3(2) XOR din3(3) XOR
din3(4) XOR din3(5) XOR din3(6) XOR din3(7) XOR Parin(3);
Synd(4) <= din4(0) XOR din4(1) XOR din4(2) XOR din4(3) XOR
din4(4) XOR din4(5) XOR din4(6) XOR din4(7) XOR Parin(4);
process(Datain, Parin, synd, P0)
begin
NE <= '1';
DED <= '0';
SEC <= '0';
Dataout <= Datain;
Parout <= Parin;
if (synd = "0000") then
IF (P0 = '0') then
--Dataout <= Datain;
--NE <= '1';
--DED <= '0';
--SEC <= '0';
--Parout <= Parin;
null;
elsif (P0 = '1') then --single error
NE <= '0';
DED <= '0';
SEC <= '1';
case synd is
when "0000" => Parout(0) <= NOT Parin(0);
when "0001" => Parout(1) <= NOT Parin(1);
when "0010" => Parout(2) <= NOT Parin(2);
when "0011" => Dataout(0) <= NOT Datain(0);
when "0100" => Parout(3) <= NOT parin(3);
when "0101" => Dataout(1) <= NOT Datain(1);
when "0110" => Dataout(2) <= NOT Datain(2);
when "0111" => Dataout(3) <= NOT Datain(3);
when "1000" => parout(4) <= parin(4);
when "1001" => Dataout(4) <= NOT Datain(4);
when "1010" => Dataout(5) <= NOT Datain(5);
when "1011" => Dataout(6) <= NOT Datain(6);
when "1100" => Dataout(7) <= NOT Datain(7);
when others => null;
end case;
--Dataout <= "00000000"; -- these lines override all calculations
--Parout <= "00000"; -- from previous case statement
end if;
elsif (P0 = '0') then
if (synd /= "0000") then
NE <= '0';
DED <= '1';
SEC <= '0';
Dataout <= "00000000";
Parout <= "00000";
end if;
end if;
end process;
end beh;
ieee库;
使用ieee.std_logic_1164.all;
实体hamdec8是
港口(
数据输入:标准逻辑向量(7到0);
parin:标准逻辑向量(4到0);
数据输出:输出标准逻辑向量(7到0);
输出:输出标准逻辑向量(4到0);
NE:输出标准逻辑;
DED:输出标准逻辑;
第二节:输出标准逻辑
);
第8章结束;
汉德街8号的建筑是
常数MaskP1:std_逻辑_向量(7到0):=“01011011”;
常数MaskP2:std_逻辑_向量(7到0):=“01101101”;
常数MaskP3:std_逻辑_向量(7到0):=“10001110”;
常数MaskP4:std_逻辑_向量(7到0):=“11110000”;
信号synd:std_逻辑_向量(4到1);
信号P0:std_逻辑;
信号din1、din2、din3、din4:std_逻辑_向量(7到0)--保存数据和maskp
开始
P0这个代码是怎么回事
IF (P0 = '0') then
-- commented out stuff
[...]
null;
elsif (P0 = '1') then --single error
[...]
end if;
为什么不直接使用:
if p0 = '1' then
[...]
end if;
或者至少
if p0 = '0' then
[stuff for when p0 is '0']
else
[stuff for when p0 is not '0']
end if;