在VHDL中如何在时钟中暂停2Hz？
我是VHDL新手，我需要在VHDL程序中为计数器项目暂停2Hz或0.5Hz 另一方面，我有以下代码：在VHDL中如何在时钟中暂停2Hz？,vhdl,clock,intel-fpga,Vhdl,Clock,Intel Fpga,我是VHDL新手，我需要在VHDL程序中为计数器项目暂停2Hz或0.5Hz 另一方面，我有以下代码： architecture behavior of Counter is signal q: std_logic_vector(7 downto 0); begin process(clock, choose) begin if clear = '1' then q <= q - q; else if rising_edge(clock
architecture behavior of Counter is
signal q: std_logic_vector(7 downto 0);
begin
process(clock, choose)
begin
if clear = '1' then
q <= q - q;
else
if rising_edge(clock) then
-- when choose is '1', the process if for increment
if(choose = '1') then
case incodec is
when "001" => q <= q + 1;
when "011" => q <= q + 10;
when "111" => q <= q + 11;
when others => q <= q;
end case;
-- when choose is '0', the process if for decrement
elsif choose = '0' then
case incodec is
when "001" => q <= q - 1;
when "011" => q <= q - 10;
when "111" => q <= q - 11;
when others => q <= q;
end case;
end if;
end if;
end if;
case q(7 downto 4) is
-- 6543210
when "0000" => hex7 <= "1000000"; --0
when "0001" => hex7 <= "1111001"; --1
when "0010" => hex7 <= "0100100"; --2
when "0011" => hex7 <= "0110000"; --3
when "0100" => hex7 <= "0011001"; --4
when "0101" => hex7 <= "0010010"; --5
when "0110" => hex7 <= "0000010"; --6
when "0111" => hex7 <= "1111000"; --7
when "1000" => hex7 <= "0000000"; --8
when "1001" => hex7 <= "0010000"; --9
when "1010" => hex7 <= "0001000"; --10/A
when "1011" => hex7 <= "0000011"; --11/B/b
when "1100" => hex7 <= "1000110"; --12/C
when "1101" => hex7 <= "0100001"; --13/D/d
when "1110" => hex7 <= "0000110"; --14/E
when "1111" => hex7 <= "0001110"; --15/F
when others => hex7 <= "0111111"; -- -
end case;
case q(3 downto 0) is
-- 6543210
when "0000" => hex6 <= "1000000"; --0
when "0001" => hex6 <= "1111001"; --1
when "0010" => hex6 <= "0100100"; --2
when "0011" => hex6 <= "0110000"; --3
when "0100" => hex6 <= "0011001"; --4
when "0101" => hex6 <= "0010010"; --5
when "0110" => hex6 <= "0000010"; --6
when "0111" => hex6 <= "1111000"; --7
when "1000" => hex6 <= "0000000"; --8
when "1001" => hex6 <= "0010000"; --9
when "1010" => hex6 <= "0001000"; --10/A
when "1011" => hex6 <= "0000011"; --11/B/b
when "1100" => hex6 <= "1000110"; --12/C
when "1101" => hex6 <= "0100001"; --13/D/d
when "1110" => hex6 <= "0000110"; --14/E
when "1111" => hex6 <= "0001110"; --15/F
when others => hex6 <= "0111111"; -- -
end case;
end behavior
确实有11个这样的错误。首先，请向我们展示完整的代码，因为错误可能在shows代码段之外。第二，为什么在递增的数字中有这么多前导零？第三，在其他情况下，您不需要将q分配给q，因为这是一个计时过程，一些合成器可能会对这种编码风格感到恼火。您是否知道00000011是一个值为11的整数文字，而不是一个值为3的二进制数？关于暂停的代码如何与您的代码片段相关联？暂停不是以赫兹为单位的，而是以秒为单位的，因为它是一个时间而不是频率。其他情况的问题是，当我编译项目时，向我显示以下错误：错误10313:VHDL Case语句计数器错误。vhd29:Case语句选择必须覆盖表达式的所有可能值是，其他必须存在，但这并不意味着您需要的是11个这样的错误。首先，请向我们展示完整的代码，因为这些错误可能在shows代码片段之外。第二，为什么在递增的数字中有这么多前导零？第三，在其他情况下，您不需要将q分配给q，因为这是一个计时过程，一些合成器可能会对这种编码风格感到恼火。您是否知道00000011是一个值为11的整数文字，而不是一个值为3的二进制数？关于暂停的代码如何与您的代码片段相关联？暂停不是以赫兹为单位的，而是以秒为单位的，因为它是时间而不是频率。其他情况的问题是，当我编译项目时，向我显示以下错误：错误10313:VHDL Case语句erro
r at Counter.vhd29:Case语句选择必须覆盖表达式的所有可能值是的，其他值必须存在，但这并不意味着您需要q这个答案如何回答我如何在VHDL中在时钟中暂停2Hz？@user1155120在编写答案的第1部分以使其代码正常工作时，我解决了他关于一个国家的含蓄问题，这个国家如果处于上升边缘的话，就不会被排斥在外。当他澄清他的问题时，我仍然希望能编辑第二部分。这如何回答我如何用VHDL在时钟中暂停2Hz？@user1155120在编写第1部分的答案时，为了让他的代码正常工作，我解决了他关于上升沿时不在外部保持的状态的隐含问题。当他澄清他的问题时，我仍然希望能编辑出第二部分。
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Counter is
-- ...
end entity;
architecture behavior of Counter is
signal q : unsigned(7 downto 0) := (others => '0');
begin
process(clock, clear)
variable decoded : positive;
variable hex : std_logic_vector(13 downto 0);
begin
case incodec is
when "001" => decoded := 1;
when "011" => decoded := 2;
when "111" => decoded := 3;
when others => decoded := 0;
end case;
if clear = '1' then
q <= (others => '0');
elsif rising_edge(clock) then
if(choose = '1') then -- when choose is '1', the process if for increment
q <= q + decoded;
elsif (choose = '0') then -- when choose is '0', the process if for decrement
q <= q - decoded;
end if;
end if;
for i in 0 to 1 loop
case q(i*4+7 downto i*4) is -- 6543210
when "0000" => hex(i*7+6 downto i*7) := "1000000"; --0
when "0001" => hex(i*7+6 downto i*7) := "1111001"; --1
when "0010" => hex(i*7+6 downto i*7) := "0100100"; --2
when "0011" => hex(i*7+6 downto i*7) := "0110000"; --3
when "0100" => hex(i*7+6 downto i*7) := "0011001"; --4
when "0101" => hex(i*7+6 downto i*7) := "0010010"; --5
when "0110" => hex(i*7+6 downto i*7) := "0000010"; --6
when "0111" => hex(i*7+6 downto i*7) := "1111000"; --7
when "1000" => hex(i*7+6 downto i*7) := "0000000"; --8
when "1001" => hex(i*7+6 downto i*7) := "0010000"; --9
when "1010" => hex(i*7+6 downto i*7) := "0001000"; --10/A
when "1011" => hex(i*7+6 downto i*7) := "0000011"; --11/b
when "1100" => hex(i*7+6 downto i*7) := "1000110"; --12/C
when "1101" => hex(i*7+6 downto i*7) := "0100001"; --13/d
when "1110" => hex(i*7+6 downto i*7) := "0000110"; --14/E
when "1111" => hex(i*7+6 downto i*7) := "0001110"; --15/F
when others => hex(i*7+6 downto i*7) := "0111111"; -- -
end case;
end loop;
hex7 <= hex(13 downto 7);
hex6 <= hex(6 downto 0);
end process;
end architecture;