属性事件需要vhdl中8位乘法器中的静态信号前缀

我正在实现一个乘法器，其中我将a（8位）和B（8位）相乘，并将结果存储在S。输出S所需的位数为16位。S具有较高的SH部分和较低的SL部分。每次我移位时，都会执行添加操作 我的控制器部件出现以下错误：- 属性事件需要静态信号前缀 未声明。 “**”需要2个参数

我的密码是：-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity  PIPO is
port (reset: in  std_logic ;
        B:IN STD_LOGIC_VECTOR (7 downto 0 );
        LOAD:in  std_logic ;
        SHIFT:in  std_logic ;
        ADD:in  std_logic ;
        Sum:IN STD_LOGIC_VECTOR (7 downto 0 );
        C_out:in  std_logic ;
        CLK:in  std_logic ;
        result: out  STD_LOGIC_VECTOR (15 downto 0) ;
        LSB:out std_logic ;
        TB:out std_logic_vector (7 downto 0) );
    end ;

architecture rtl OF PIPO is
    signal temp1 : std_logic_vector(15 downto 0);
    ----temp2 -add 
    signal temp2 : std_logic ;
begin
process (CLK, reset)
  begin
    if reset='0' then
        temp1<= (others =>'0');
        temp2<= '0';
     elsif (CLK'event and CLK='1') then
        if LOAD ='1'  then
        temp1(7 downto 0) <= B; 
        temp1(15 downto 8) <= (others => '0');
    end if ;

    if ADD= '1' then
    temp2 <='1';
    end if;
    if SHIFT= '1' then
        if ADD= '1' then
        ------adder result ko add n shift

        temp2<= '0';
        temp1<=C_out & Sum & temp1( 7 downto 1 );

        else 
        ----only shift
        temp1<= '0' &  temp1( 15 downto 1 );
       end if;
    end if;

end if;
  end process;

  LSB <=temp1(0);
  result<=temp1( 15 downto 0 );
  TB <=temp1(15 downto 8);
    end architecture rtl;
-------------------------------------------
-------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

    entity Controller is
Port ( ADD :OUT STD_LOGIC;
            SHIFT:OUT STD_LOGIC;
            LOAD:OUT STD_LOGIC;
            STOP:OUT STD_LOGIC;
            STRT:IN STD_LOGIC;
            LSB:IN STD_LOGIC;
            CLK:IN STD_LOGIC;
            reset:IN STD_LOGIC ); 
    end ;   
architecture rtl OF Contoller is
---RTL level code is inherently synchronous 
signal count : unsigned (2 downto 0);

----differnt states 
type state_typ is ( IDLE, INIT, TEST, ADDs, SHIFTs );
signal state : state_typ;


begin
--controller : process (ADD,SHIFT,LOAD,STOP,STRT,LSB,CLK,reset)
process (state)--(CLK, reset,ADD,SHIFT,LOAD,STOP,STRT,LSB)
  begin
    if reset='0' then
      state <= IDLE;
      count <= "000";
    elsif (CLK'event and CLK='1') then

            case state is
        when IDLE =>
          if STRT = '1' then
         --- if STRT = '1' then
            state <= INIT;
          else
            state <= IDLE;
          end if;
        when INIT =>
          state <= TEST;
        when TEST =>
          if LSB = '0' then
            state <= SHIFTs;
          else
            state <= ADDs;
          end if;
        when ADDs =>
          state <= SHIFTs;

        when SHIFTs =>
          if count = "111" then  
            count <= "000";      
            state <= IDLE;          
          else
            count<= std_logic_vector(unsigned(count) + 1);
            state <= TEST;
          end if;
      end case;
    end if;
  end process ;
  STOP <= '1' when state = IDLE else '0';
  ADD <= '1' when state = ADDs else '0';
  SHIFT <= '1' when state = SHIFTs else '0';
  LOAD <= '1' when state = INIT else '0';
end architecture rtl;




----------------------------------------------
--------------------------------------------


---multiplicand
library ieee;
use ieee.std_logic_1164.all;    
entity multiplicand is 
port (A : in std_logic(7 downto 0);
        reset :in std_logic;
        LOAD : in std_logic;
        TA : OUT STD_LOGIC(7 downto 0);
        CLK : in std_logic );
    end entity;     
architecture rtl OF multiplicand is
begin 
process (CLK, reset)
  begin
    if reset='0' then
      TA <= (others =>'0');  -- initialize 

    elsif (CLK'event and CLK='1') then
      if LOAD_cmd = '1' then
     TA(7 downto 0) <= A_in;  -- load B_in into register
      end if;
end if ;

end process;
end architecture rtl;   



------------------------------------------------------
------------------------------------------------------
---Full Adder
library ieee;
use ieee.std_logic_1164.all;
entity  Full_Adder  is
port (A     : in  std_logic;
      B     : in  std_logic;
      C_in  : in  std_logic;
      Sum   : out std_logic ;
      C_out : out std_logic);
end;
architecture  struc  of  Full_Adder  is
begin
Sum <= A xor B xor C_in;
C_out <= (A and B) or (A and C_in) or (B and C_in);
end struc;
------------------------------------------------------------
-------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Adder is
    Port ( TA : in  STD_LOGIC_VECTOR (7 downto 0);
           TB : in  STD_LOGIC_VECTOR (7 downto 0);
           Sum : out  STD_LOGIC_VECTOR (7 downto 0);
           C_in : in STD_LOGIC;
              C_out : out  STD_LOGIC);
end Adder;


architecture struc of Adder is
component Full_Adder is  
      port(A     : in  std_logic;
            B     : in  std_logic;
            C_in  : in  std_logic;
            Sum   : out std_logic ;
            C_out : out std_logic);
   end component;

    signal C: std_logic_vector (7 downto 0); 

begin
    FA0:Full_Adder port map(TA(0), TB(0), C_in,   Sum(0), C(0));
    FA1: Full_Adder port map(TA(1), TB(1), C(0),  Sum(1), C(1));
   FA3: Full_Adder port map(TA(2),TB(2), C(1),  Sum(2), C(2));
    FA4: Full_Adder port map(TA(3), TB(3), C(2),   Sum(3), C(3));
    FA5: Full_Adder port map(TA(4), TB(4), C(3),  Sum(4), C(4));
    FA6: Full_Adder port map(TA(5), TB(5), C(4),   Sum(5), C(5));
    FA7: Full_Adder port map(TA(6), TB(6), C(5),   Sum(6), C(6));
    FA8: Full_Adder port map(TA(7), TB(7), C(6),   Sum(7), C(7));

    C_out <= C(7);

end struc;
------------------------------------------------------------
------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multiplier is
    Port ( num1 : in  STD_LOGIC_VECTOR (7 downto 0);
           num2 : in  STD_LOGIC_VECTOR (7 downto 0);
           result : out  STD_LOGIC_VECTOR (15 downto 0); 
              CLK:in  std_logic ;
              reset:IN STD_LOGIC;
              STRT:IN STD_LOGIC;
              STOP:OUT STD_LOGIC );

end multiplier;

architecture rtl of Multiplier is
    signal ADD :STD_LOGIC;
    signal SHIFT :STD_LOGIC;
    signal LOAD :STD_LOGIC;
    signal LSB :STD_LOGIC;
    signal A : STD_LOGIC_VECTOR (7 downto 0);
    signal B :STD_LOGIC_VECTOR (7 downto 0);
    signal Sum:STD_LOGIC_VECTOR (7 downto 0);
    signal C_out:STD_LOGIC;

component Controller
      port (
            ADD :OUT STD_LOGIC;
            SHIFT:OUT STD_LOGIC;
            LOAD:OUT STD_LOGIC;
            STOP:OUT STD_LOGIC;
            STRT:IN STD_LOGIC;
            LSB:IN STD_LOGIC;
            CLK:IN STD_LOGIC;
            reset:IN STD_LOGIC );

         end component;     
component Adder 
        port ( 
                TA : in  STD_LOGIC_VECTOR (7 downto 0);
           TB : in  STD_LOGIC_VECTOR (7 downto 0);
           Sum : out  STD_LOGIC_VECTOR (7 downto 0);
           C_in : in STD_LOGIC;
              C_out : out  STD_LOGIC);

         end component;
component PIPO
    port (reset: in  std_logic ;
        B:IN STD_LOGIC_VECTOR (7 downto 0 );
        LOAD:in  std_logic ;
        SHIFT:in  std_logic ;
        ADD:in  std_logic ;
        Sum:IN STD_LOGIC_VECTOR (7 downto 0 );
        C_out:in  std_logic ;
        CLK:in  std_logic ;
        result: out  STD_LOGIC_VECTOR (15 downto 0) ;
        LSB:out std_logic ;
        TB:out std_logic );

end component;
    component multiplicand 
    port (A : in std_logic (7 downto 0);
        reset :in std_logic;
        LOAD : in std_logic;
        TA : OUT STD_LOGIC(7 downto 0);
        CLK : in std_logic );
end component ;
begin

inst_Controller: Controller
port map (ADD => ADD,
            SHIFT =>SHIFT,
            LOAD =>LOAD ,
            STOP =>STOP,
            STRT =>STRT,
            LSB =>LSB ,
            CLK =>CLK ,
            reset =>reset
            );
inst_multiplicand :multiplicand     
port map (A =>A,
        reset=>reset,
        LOAD =>LOAD,
        TA => TA(7 downto 0),
        CLK => CLK
            );      


inst_PIPO :PIPO
port map ( reset => reset,
        B => B ,
        LOAD =>LOAD,
        SHIFT=>SHIFT,
        ADD=>ADD,
        Sum=>Sum,
        C_out=>C_out,
        CLK=>CLK,
        result=>result,
        LSB=>LSB,
        TB=>TB
            );

inst_Full_Adder : Full_Adder
        port map ( TA => TA,
           TB =>TB,
           Sum=>Sum ,
           C_in=>C_in,
              C_out=>C_out 
              );


end rtl;

IEEE库；
使用IEEE.STD_LOGIC_1164.ALL；
使用ieee.std_logic_arith.all；
使用ieee.std_logic_unsigned.all；
实体PIPO是
端口（复位：在std_逻辑中；
B：标准逻辑向量（7到0）；
负载：在标准逻辑中；
移位：在标准逻辑中；
添加：标准逻辑中；
总和：标准逻辑向量（7到0）；
C_out：标准逻辑中；
CLK：标准逻辑中；
结果：输出标准逻辑向量（15到0）；
LSB：输出标准逻辑；
TB:out标准逻辑向量（7到0）；
结束；
PIPO的rtl体系结构是
信号temp1:std_逻辑_向量（15到0）；
----临时2-添加
信号temp2:std_逻辑；
开始
过程（时钟、复位）
开始
如果reset='0'，则
temp1'0'）；
临时2
如果STRT='1'，则
---如果STRT='1'，则
声明你会为此而自责：

elsif (CLK 'event and CLK ='1') then

应该是：

elsif (CLK'event and CLK ='1') then

看到区别了吗

更好的是：

elsif rising_edge(CLK) then

实际上，CLK和撇号/勾号之间的空格并不重要

david_koontz@Macbook: token_test
elsif (CLK 'event and CLK ='1') then
KEYWD_ELSIF             (151)   elsif
DELIM_LEFT_PAREN        (  9)   (
IDENTIFIER_TOKEN        (128)   CLK
DELIM_APOSTROPHE        (  8)   '
IDENTIFIER_TOKEN        (128)   event
KEYWD_AND               (134)   and
IDENTIFIER_TOKEN        (128)   CLK
DELIM_EQUAL             ( 25)   =
CHAR_LIT_TOKEN          (  2)   '1'
DELIM_RIGHT_PAREN       ( 10)   )
KEYWD_THEN              (211)   then

给出与以下相同的答案：

david_koontz@Macbook: token_test
elsif (CLK'event and CLK ='1') then
KEYWD_ELSIF             (151)   elsif
DELIM_LEFT_PAREN        (  9)   (
IDENTIFIER_TOKEN        (128)   CLK
DELIM_APOSTROPHE        (  8)   '
IDENTIFIER_TOKEN        (128)   event
KEYWD_AND               (134)   and
IDENTIFIER_TOKEN        (128)   CLK
DELIM_EQUAL             ( 25)   =
CHAR_LIT_TOKEN          (  2)   '1'
DELIM_RIGHT_PAREN       ( 10)   )
KEYWD_THEN              (211)   then

在vhdl中，没有需要缺少空格的词法元素解析。（对不起，拉塞尔）

纠正代码的其他语法歧义（见下文，missing context子句，架构声明中的控制器拼写错误，
count
同时用作标量和数组子类型），会导致两个不同的VHDL分析器吞噬CLK和“刚刚好”之间的空间

问题在于您正在使用的工具实际上不符合标准，或者您呈现的问题代码实际上不代表生成错误的代码。如果是一个不兼容的工具，这很可能是一个你可以接受的缺点，尽管可能有更多的事情更让人讨厌

大卫_koontz@Macbook：ghdl-一个控制器。vhdl

大卫_koontz@Macbook：nvc-控制器。vhdl

大卫_koontz@Macbook:

（没有错误，在ghdl中也没有测试台，nvc不允许顶级端口，这是标准允许的）

ieee库；
使用ieee.std_logic_1164.all；
使用ieee.numeric_std.all；
实体控制器是
港口（
加：输出标准逻辑；
移位：输出标准逻辑；
加载：输出标准逻辑；
停止：输出标准逻辑；
STRT：在标准逻辑中；
LSB：标准逻辑中；
CLK：标准逻辑中；
复位：在标准逻辑中
); 
终端实体；
介绍了控制器的rtl体系结构
---RTL级代码本质上是同步的
信号计数：标准逻辑向量（2到0）；
----不同状态
类型状态类型为（空闲、初始化、测试、添加、移位）；
信号状态：状态\典型；
开始
诺拉贝尔：
过程（时钟、复位）
开始
如果reset='0'，则
状态您似乎在该过程中丢失了一个clk条目

将行更改为：

process (state)--(CLK, reset,ADD,SHIFT,LOAD,STOP,STRT,LSB)

全文如下：

process (clk, reset)

'event
没有前缀作为错误消息，Russell告诉您。此外，实体和体系结构声明之间的实体名称不匹配，并且您正在将Count初始化为。。。显然是一个字符串，而不是一个整数。哪个VHDL工具给出了投诉？它似乎不符合VHDL标准。
process (clk, reset)