VHDL“此处不允许非共享变量声明”
我有这段代码,基本上是计算2个数的模VHDL“此处不允许非共享变量声明”,vhdl,hdl,ghdl,Vhdl,Hdl,Ghdl,我有这段代码,基本上是计算2个数的模 library IEEE; use ieee.numeric_bit.all; entity resto is port (clock , reset : in bit ; inicio : in bit ; fim : out bit ; dividendo , divisor : in bit_vector (15 downto 0) ; resto : out bit_vect
library IEEE;
use ieee.numeric_bit.all;
entity resto is
port (clock , reset : in bit ;
inicio : in bit ;
fim : out bit ;
dividendo , divisor : in bit_vector (15 downto 0) ;
resto : out bit_vector (15 downto 0)
) ;
end resto;
architecture processo of resto is
variable dividendovar : integer range 0 to 15;
begin
process(clock, reset) is
begin
if reset = '1' then
fim <= '0';
resto <= "0000000000000000";
elsif clock'event and clock = '1' and inicio = '1' then
dividendovar <= to_integer(unsigned(dividendo));
if (divisor = "0000000000000000") then
-- report "zero";
resto <= dividendo;
fim <= '1';
elsif (dividendovar = to_integer(unsigned(divisor))) then
-- report "menor";
-- report "dividendoaux vale "& integer'image(to_integer(unsigned(dividendoaux))) ;
resto <= "0000000000000000";
fim <= '1';
elsif (to_integer(unsigned(dividendo)) < to_integer(unsigned(divisor))) then
resto <= dividendo;
fim <= '1';
else -- comeca a subtrair
while (dividendovar > to_integer(unsigned(divisor))) loop
dividendovar := dividendovar - to_integer(unsigned(divisor));
end loop ;
resto <= bit_vector(to_unsigned(dividendovar, resto'length));
fim <= '1';
end if;
end if;
end process;
end architecture;
我得到这个错误,这里不允许非共享变量声明
我做错了什么或遗漏了什么
提前谢谢 变量应在进程内声明,因此具有受限范围
library IEEE;
use ieee.numeric_bit.all;
entity resto is
port (clock , reset : in bit ;
inicio : in bit ;
fim : out bit ;
dividendo , divisor : in bit_vector (15 downto 0) ;
resto : out bit_vector (15 downto 0)
) ;
end resto;
architecture processo of resto is
begin
process(clock, reset) is
variable dividendovar : integer range 0 to 15;
begin
if reset = '1' then
fim <= '0';
resto <= "0000000000000000";
elsif clock'event and clock = '1' and inicio = '1' then
dividendovar <= to_integer(unsigned(dividendo));
if (divisor = "0000000000000000") then
-- report "zero";
resto <= dividendo;
fim <= '1';
elsif (dividendovar = to_integer(unsigned(divisor))) then
-- report "menor";
-- report "dividendoaux vale "& integer'image(to_integer(unsigned(dividendoaux))) ;
resto <= "0000000000000000";
fim <= '1';
elsif (to_integer(unsigned(dividendo)) < to_integer(unsigned(divisor))) then
resto <= dividendo;
fim <= '1';
else -- comeca a subtrair
while (dividendovar > to_integer(unsigned(divisor))) loop
dividendovar := dividendovar - to_integer(unsigned(divisor));
end loop ;
resto <= bit_vector(to_unsigned(dividendovar, resto'length));
fim <= '1';
end if;
end if;
end process;
end architecture;
如评论中所述,在VHDL2002标准之前,全球共享变量一直可用。如果还需要的话,我认为他们现在应该得到保护。但到目前为止,我遇到了一个需要变量的用例
在我所有的设计中,只要有可能,我都更喜欢信号而不是变量。像这样的共享变量只有在VHDL 1993中才允许使用。从VHDL 2002开始,共享变量必须是受保护的类型,目前我所知道的任何工具都不能合成该类型。OP是一个新手。最好更新示例以显示流程中声明的变量。如@Tricky said,普通类型的共享变量已被弃用并由VHDL-2000删除,VHDL-2000已被VHDL-2002取代。因此,请从您的解决方案中删除共享变量。同意,但代码仍然是可合成的,只是不兼容。..@po.pe WRT如果您更喜欢信号而不是变量,此问题说明了哪里需要变量,如果您必须在不经过时间的情况下迭代对象,那么您需要一个立即更新的对象—因此,需要一个变量。while循环不太可能是可合成的,算法使用的减法比可能需要的要多。整个错误消息包括一个行号和指向保留字变量的字符计数。非共享变量声明只能作为子程序参数声明、子程序声明项或流程声明项出现。您声明的信号分割作为块声明项。仅仅更改名称并声明它为类变量是不够的。您是否打算将divendovar设置为0到15之间的4位范围?我猜它是16位。另一种想法是,你的while循环可能是不可合成的。您是否想过使用for循环并可能迭代不超过N次,其中N是除数中的位数?
library IEEE;
use ieee.numeric_bit.all;
entity resto is
port (clock , reset : in bit ;
inicio : in bit ;
fim : out bit ;
dividendo , divisor : in bit_vector (15 downto 0) ;
resto : out bit_vector (15 downto 0)
) ;
end resto;
architecture processo of resto is
begin
process(clock, reset) is
variable dividendovar : integer range 0 to 15;
begin
if reset = '1' then
fim <= '0';
resto <= "0000000000000000";
elsif clock'event and clock = '1' and inicio = '1' then
dividendovar <= to_integer(unsigned(dividendo));
if (divisor = "0000000000000000") then
-- report "zero";
resto <= dividendo;
fim <= '1';
elsif (dividendovar = to_integer(unsigned(divisor))) then
-- report "menor";
-- report "dividendoaux vale "& integer'image(to_integer(unsigned(dividendoaux))) ;
resto <= "0000000000000000";
fim <= '1';
elsif (to_integer(unsigned(dividendo)) < to_integer(unsigned(divisor))) then
resto <= dividendo;
fim <= '1';
else -- comeca a subtrair
while (dividendovar > to_integer(unsigned(divisor))) loop
dividendovar := dividendovar - to_integer(unsigned(divisor));
end loop ;
resto <= bit_vector(to_unsigned(dividendovar, resto'length));
fim <= '1';
end if;
end if;
end process;
end architecture;