Vhdl 添加两个无符号（8位）并将结果存储在9位无符号

我尝试用进位实现一个简单的8位加法器来测试GHDL和gtkwave。 不幸的是，加法器和tb的VHDL代码以及控制台输出都被附加在一起，因此加法执行错误。 有人知道为什么会发生这种错误吗？ 如果我删除resize函数和carry位，并将“myBuffer”压缩到8位，错误仍然会发生

问候

加法器：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity adder is
    port(
    clk : in std_logic;
    opA, opB :in std_logic_vector(7 downto 0);
    c :out std_logic;
    result :out std_logic_vector(7 downto 0)
    );
end entity adder;

architecture rtl of adder is
    --signals
    signal myBuffer : unsigned(8 downto 0);
begin
    add : process(clk, opA, opB)
    variable c_buf : std_logic := '0';
    begin  
        --on rising edge
        if(clk'event and clk = '1') then
            myBuffer <= resize(unsigned(opA) + unsigned(opB), myBuffer'length);
            --result <= myBuffer(7 downto 0);
            c_buf := myBuffer(8);
            assert c_buf = '1' report "carry detected" severity note;
            report "opA = "&positive'image(to_integer(unsigned(opA)));
            report "opB = "&positive'image(to_integer(unsigned(opB)));
            report "expected result = "&positive'image(to_integer(unsigned(opA)+unsigned(opB)));
            report "myBuffer = "&positive'image(to_integer(myBuffer));
            c <= c_buf;
        end if;
    end process;

end architecture;

---

这里有几个问题

---

由于分配信号的方式，您看到报告的mybuffer落后于一次计算。当你分配一个信号时，例如：

a啊，现在我记得我读到了一些关于变量分配和进程内信号分配差异的内容，谢谢！！顺便说一句，它现在可以工作了。同时也感谢关于未签名添加和正面图像的提示，非常有趣！
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

--library adderLib;

entity adder_tb is
end entity;

architecture rtl of adder_tb is

    type data is array(3 downto 0) of std_logic_vector(7 downto 0);

    --components
    component adder is
        port(
        clk : in std_logic;
        opA, opB :in std_logic_vector(7 downto 0);
        c :out std_logic;
        result :out std_logic_vector(7 downto 0)
        );
    end component;

    --for all: adder use entity adderLib.adder;

signal clk : std_logic := '0';
signal c : std_logic;
signal result : std_logic_vector(7 downto 0);
signal InOpA : std_logic_vector(7 downto 0);
signal InOpB : std_logic_vector(7 downto 0);
constant opA : data :=(0=>x"08",1=>x"09",2=>x"0A",3=>x"0B");
constant opB : data :=(0=>x"FF",1=>x"01",2=>x"02",3=>x"03");


begin

    --apply test signals & gen clock
   process
    variable iteration :integer := 0;
    begin
        for i in opA'range loop
            InOpA <= opA(i);
            InOpB <= opB(i);
            clk <= not clk;
            wait for 5 ns;
            clk <= not clk; 
            wait for 5 ns;
            report "iteration";
        end loop;
        
    end process;

    --connect component
    adierer: adder
        port map(
        clk => clk,
        opA => InOpA,
        opB => InOpB,
        c => c,
        result => result
        );

end rtl ;

adder.vhd:26:13:@0ms:(assertion note): carry detected
adder.vhd:27:13:@0ms:(report note): opA = 11
adder.vhd:28:13:@0ms:(report note): opB = 3
adder.vhd:29:13:@0ms:(report note): expected result = 14
../../../src/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
adder.vhd:30:13:@0ms:(report note): myBuffer = 0
adder_tb.vhd:48:13:@10ns:(report note): iteration
adder.vhd:26:13:@10ns:(assertion note): carry detected
adder.vhd:27:13:@10ns:(report note): opA = 10
adder.vhd:28:13:@10ns:(report note): opB = 2
adder.vhd:29:13:@10ns:(report note): expected result = 12
adder.vhd:30:13:@10ns:(report note): myBuffer = 14
adder_tb.vhd:48:13:@20ns:(report note): iteration
adder.vhd:26:13:@20ns:(assertion note): carry detected
adder.vhd:27:13:@20ns:(report note): opA = 9
adder.vhd:28:13:@20ns:(report note): opB = 1
adder.vhd:29:13:@20ns:(report note): expected result = 10
adder.vhd:30:13:@20ns:(report note): myBuffer = 12
adder_tb.vhd:48:13:@30ns:(report note): iteration
adder.vhd:26:13:@30ns:(assertion note): carry detected
adder.vhd:27:13:@30ns:(report note): opA = 8
adder.vhd:28:13:@30ns:(report note): opB = 255
adder.vhd:29:13:@30ns:(report note): expected result = 7
adder.vhd:30:13:@30ns:(report note): myBuffer = 10
adder_tb.vhd:48:13:@40ns:(report note): iteration
adder.vhd:26:13:@40ns:(assertion note): carry detected
adder.vhd:27:13:@40ns:(report note): opA = 11
adder.vhd:28:13:@40ns:(report note): opB = 3
adder.vhd:29:13:@40ns:(report note): expected result = 14
adder.vhd:30:13:@40ns:(report note): myBuffer = 7
adder_tb.vhd:48:13:@50ns:(report note): iteration
adder.vhd:26:13:@50ns:(assertion note): carry detected
adder.vhd:27:13:@50ns:(report note): opA = 10
adder.vhd:28:13:@50ns:(report note): opB = 2
adder.vhd:29:13:@50ns:(report note): expected result = 12
adder.vhd:30:13:@50ns:(report note): myBuffer = 14
adder_tb.vhd:48:13:@60ns:(report note): iteration
adder.vhd:26:13:@60ns:(assertion note): carry detected
adder.vhd:27:13:@60ns:(report note): opA = 9
adder.vhd:28:13:@60ns:(report note): opB = 1
adder.vhd:29:13:@60ns:(report note): expected result = 10
adder.vhd:30:13:@60ns:(report note): myBuffer = 12
adder_tb.vhd:48:13:@70ns:(report note): iteration
adder.vhd:26:13:@70ns:(assertion note): carry detected
adder.vhd:27:13:@70ns:(report note): opA = 8
adder.vhd:28:13:@70ns:(report note): opB = 255
adder.vhd:29:13:@70ns:(report note): expected result = 7
adder.vhd:30:13:@70ns:(report note): myBuffer = 10
adder_tb.vhd:48:13:@80ns:(report note): iteration
adder.vhd:26:13:@80ns:(assertion note): carry detected
adder.vhd:27:13:@80ns:(report note): opA = 11
adder.vhd:28:13:@80ns:(report note): opB = 3
adder.vhd:29:13:@80ns:(report note): expected result = 14
adder.vhd:30:13:@80ns:(report note): myBuffer = 7
adder_tb.vhd:48:13:@90ns:(report note): iteration
adder.vhd:26:13:@90ns:(assertion note): carry detected
adder.vhd:27:13:@90ns:(report note): opA = 10
adder.vhd:28:13:@90ns:(report note): opB = 2
adder.vhd:29:13:@90ns:(report note): expected result = 12
adder.vhd:30:13:@90ns:(report note): myBuffer = 14
adder_tb.vhd:48:13:@100ns:(report note): iteration
adder.vhd:26:13:@100ns:(assertion note): carry detected
adder.vhd:27:13:@100ns:(report note): opA = 9
adder.vhd:28:13:@100ns:(report note): opB = 1
adder.vhd:29:13:@100ns:(report note): expected result = 10
adder.vhd:30:13:@100ns:(report note): myBuffer = 12
./adder_tb:info: simulation stopped by --stop-time