Vhdl 组件实例“d0:or2”没有默认绑定。（组件端口“out1”不在实体上。）

我正在尝试使用结构代码在VHDL中构建一个异或门。我使用其他方法构建了相同的门，以使用测试台比较输出

这是xor_structural.vhdl文件。我自己构建了and、or和nand。我不认为它们需要放在一个单独的文件中，因为它编译得很好。该文件和测试台编译没有问题，但我不能运行模拟

测试台和其他模拟工作得很好，但是当我尝试运行模拟时，我得到以下错误

我想我遗漏了一些关于结构代码的东西

vsim work.antivalenz_tb
# vsim work.antivalenz_tb 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(51): (vopt-3473) Component instance "u0 : nand2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(52): (vopt-3473) Component instance "u1 : nand2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(53): (vopt-3473) Component instance "u2 : nand2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(54): (vopt-3473) Component instance "u3 : nand2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(55): (vopt-3473) Component instance "u4 : nand2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(56): (vopt-3473) Component instance "u5 : nand2" is not bound.
# ** Error: /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(51): No default binding for component instance "u0 : nand2".
#  (Component port "out1" is not on the entity.)
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(57): (vopt-3473) Component instance "u6 : nand2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(59): (vopt-3473) Component instance "d0 : or2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(60): (vopt-3473) Component instance "d1 : or2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(61): (vopt-3473) Component instance "d2 : or2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(62): (vopt-3473) Component instance "d3 : or2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(63): (vopt-3473) Component instance "d4 : or2" is not bound.
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(64): (vopt-3473) Component instance "d5 : or2" is not bound.
# ** Error: /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(59): No default binding for component instance "d0 : or2".
#  (Component port "out1" is not on the entity.)
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(65): (vopt-3473) Component instance "d6 : or2" is not bound.
# ** Error: /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(67): No default binding for component instance "x1 : and2".
#  (Component port "out1" is not on the entity.)
# ** Warning: [1] /afs/tu-berlin.de/home/k/kekellerncsu/irb-ubuntu/digsys/aufgaben/01/antivalenz-Struktureben.vhd(67): (vopt-3473) Component instance "x1 : and2" is not bound.
# Optimization failed
# Error loading design

Xor_struktur.vhdl 实体2是 端口A、B：以位为单位； Y：输出位； 终端实体和2

architecture logic of and2 is
begin
   Y <= (A and B);
end architecture logic;

entity or2 is
port(A, B : in  bit;
Y    : out bit);
end entity or2;

architecture logic of or2 is
begin
   Y <= A or B;
end architecture logic;

entity nand2 is
port (A, B : in bit;
Y    :  out bit);
end entity nand2;   

architecture logic of nand2 is
begin
Y <= not(A and B);
end architecture logic; 

entity antivalenz_struktur is
port ( a , b : in bit_vector(0 to 3) ;
      Y : out bit ) ;
end entity antivalenz_struktur ;

architecture struktur of antivalenz_struktur is
   component and2
        port (a, b: in bit;
            out1: out bit);
   end component;
   component nand2
        port (a, b: in bit;
            out1: out bit);
   end component;
   component or2
        port (a, b: in bit;
            out1: out bit);
   end component;
signal s0,s1,s2,s3,s4,s5,s6,s7,nand_out,a0,a1,a2,a3,a4,a5,a6,a7,or_out:bit;
begin   
   U0: nand2 port map (a(0),b(0),s0);
   U1: nand2 port map (a(1),b(1),s1);
   U2: nand2 port map (a(2),b(2),s2);
   U3: nand2 port map (a(3),b(3),s3);
   U4: nand2 port map (s0,s1,s4);
   U5: nand2 port map (s2,s3,s5);
   U6: nand2 port map (s4,s5,nand_out);

   D0: or2 port map (a(0),b(0),a0);
   D1: or2 port map (a(1),b(1),a1);
   D2: or2 port map (a(2),b(2),a2);
   D3: or2 port map (a(3),b(3),a3);
   D4: or2 port map (a0,a1,a4);
   D5: or2 port map (a2,a3,a5);
   D6: or2 port map (a4,a5,or_out);

   X1: and2 port map (nand_out,or_out,Y);
end architecture struktur;

试验台文件

entity antivalenz_tb is 
end antivalenz_tb;

architecture behavior of antivalenz_tb is
    signal a, b : bit_vector (0 to 3);
    signal Y_Dataflow : bit;
    signal Y_Logic: bit;
    signal Y_Behavior: bit;
    signal Y_Structure: bit;

begin 
    dut: entity work.antivalenz_datenfluss(datenfluss)
    port map(a => a,
            b => b,
            Y => Y_Dataflow);
    dut1: entity work.antivalenz_logic(logic)
    port map(a => a,
            b => b,
            Y => Y_Logic);
    dut2: entity work.antivalenz_verhalten(behavior)
        port map(a => a,
                b => b,
                Y => Y_Behavior);
    dut3: entity work.antivalenz_struktur(struktur)
         port map(a => a,
                 b => b,
                 Y => Y_Structure);           
   a <= "0000",
          "1111" after 10 ns,
          "1010" after 20 ns,
          "0101" after 30 ns,
          "1100" after 40 ns;
   b <= "0000",
        "1111" after 10 ns,
        "0101" after 20 ns,
        "1010" after 30 ns,
        "0011" after 40 ns;
end behavior;

---

antivalenz_struktur的体系结构具有以out1作为输出名称的组件声明，但实体的端口列表中有一个名为Y的输出。您需要使组件与实体匹配，因为您在该体系结构中使用的是传统实体实例化。

@user3120471-请注意，您作为问题标题发布的错误消息表明了这一错误。有时错误消息没有什么帮助，但在这种情况下，它是正确的。