简单VHDL ALU不会在波形中显示输入或溢出

我应该写一个16位ALU。我的教授想让我们试着用

信号tmp:std_逻辑_向量（16到0）

然后在选择输入

s

的情况下，我们将：

tmp
--tmp在模拟期间，您似乎没有启用边界检查，并且代码中有五个（或更多）错误。缺少流程的敏感项，四个长度不匹配（“-”、“+”、“和”和“或”）。修好这些，就会有“U”。向我们展示波形和匹配代码。最好不要使用
std\u logic\u unsigned
（也不要使用
std\u logic\u arith
）<代码>数值\u标准

已包含正确的算法。您应该为算术指定

有符号

和

无符号

数据类型，或者甚至可以使用整数算术和转换。你的教授真的告诉过你使用

tmp吗
-- 16-Bit ALU
-- By: Logan Jordon
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
--use ieee.std_logic_arith.all;
 
entity alu16 is
    port (
        a : in std_logic_vector(15 downto 0);
        b : in std_logic_vector(15 downto 0);
        s : in std_logic_vector(1 downto 0);
        r    : out std_logic_vector(15 downto 0);
        cout : out std_logic;
        lt, eq, gt : out std_logic;
        overflow     : out std_logic
        );
end entity alu16;

architecture beh of alu16 is
signal tmp : std_logic_vector(16 downto 0);
signal add_overflow : std_logic;
signal sub_overflow : std_logic;
begin
    -- PROCESS
process(a, b, add_overflow, sub_overflow)
begin
    case s is
        --ADD
        when "00" =>
            --tmp <= conv_std_logic_vector(conv_integer(a) + conv_integer(b), 17);
            tmp <= a + b;
            overflow <= add_overflow;
        --SUB
        when "01" =>
            --tmp <= conv_std_logic_vector(conv_integer(a) - conv_integer(b), 17);
            tmp <= a - b;
            overflow <= sub_overflow;
        --AND
        when "10" =>
            tmp <= '0' & a AND b;
            overflow <= '0';
        --OR
        when "11" =>
            tmp <= '0' & a OR b;
            overflow <= '0';
        when others =>
            tmp <= "00000000000000000";
    end case;
--One-Bitters
if a > b then
    gt <= '1';
    lt <= '0';
    eq <= '0';
elsif a < b then
    lt <= '1';
    gt <= '0';
    eq <= '0';
elsif a = b then
    eq <= '1';
    lt <= '0';
    gt <= '0';
end if;
end process;

--OUTPUTS
cout <= tmp(16);
r <= tmp(15 downto 0);
add_overflow <= '1' when (a(15) = b(15)) and (a(15) /= tmp(15))
    else '0';
sub_overflow <= '1' when (a(15) = NOT b(15)) and (a(15) /= tmp(15))
    else '0';

end beh;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;

entity alu16_tb is
end alu16_tb;

architecture behavior of alu16_tb is

component ALU16
port(
        a               : in std_logic_vector(15 downto 0);
        b               : in std_logic_vector(15 downto 0);
        s               : in std_logic_vector(1 downto 0);
        r               : out std_logic_vector(15 downto 0);
        cout            : out std_logic;
        lt, eq, gt      : out std_logic;
        overflow        : out std_logic
        );
end component;

-- Signals to interface with the UUT
--  Set each of the input vectors to unique values to avoid
--  needing a process to drive them below
signal a    : std_logic_vector(15 downto 0) := "0000000000000000";
signal b    : std_logic_vector(15 downto 0) := "0000000000000000";
signal s    : std_logic_vector(1 downto 0) := "00";
signal r    : std_logic_vector(15 downto 0):= "0000000000000000";
signal cout : std_logic := '0';
signal lt   : std_logic := '0';
signal gt   : std_logic := '0';
signal eq   : std_logic := '0';
signal overflow     : std_logic := '0';
constant tick : time := 10 ns;

begin

 -- Instantiate the Unit Under Test (UUT)
 uut : ALU16 port map (
      a => a,
      b => b,
      s => s,
      r => r,
      cout => cout, 
      lt => lt,
      gt => gt,
      eq => eq,
      overflow => overflow
         );

   -- Drive selector bits
 drive_s : process
 begin
     a <= "0000000000000001";
     b <= "0000000000000010";

     wait for (tick*2);
     s <= "00";

     wait for (tick*2);
     s <= "01";

     wait for (tick*2);
     s <= "10";

     wait for (tick*2);
     s <= "11";
 end process drive_s;
end;