Vhdl 与加载modelsim仿真相关的问题

我面临一个有关Modelsim的问题。我无法在模拟中加载我的测试台。下面是我的测试台和代码

试验台

    library IEEE;
    use IEEE.numeric_std.all;
    use IEEE.std_logic_1164.all;

library work;
use work.pack1.all;

entity test_dg is
end entity;

architecture behavior of test_dg is
component digit_ext is
  generic (
    add_width : integer := 12;                                                     -- length of the adress of the node
    depth : integer := 15);
port (
  suc_add : in std_logic_vector(add_width-1 downto 0);                             -- source address
  des_add : in std_logic_vector(add_width-1 downto 0);                             -- destination address
  flg2 : out std_logic;
  flg3 : out std_logic;
  flg4 : out std_logic;
  flg5 : out std_logic;
  flg6 : out std_logic); 
end component;
signal sucadd_t: std_logic_vector(11 downto 0) := "000000000000";
signal desadd_t: std_logic_vector(11 downto 0) := "000000000000";

begin
   logic_instance: digit_ext port map (sucadd_t,desadd_t);
source_address:  process
                 begin
                 sucadd_t <= "100000000000";
                 wait for 20 ns;
                 sucadd_t <= "000000000000";
                 wait for 20 ns;
                 end process;
destination_address:  process
                 begin
                 desadd_t <= "010000000000";
                 wait for 23 ns;
                 desadd_t <= "001100000000";
                 wait for 44 ns;
                 desadd_t <= "001000000001";
                 wait for 65 ns;
                 desadd_t <= "000100100000";
                 wait for 86 ns;
                 end process;            

endsumulation:process
  begin
   wait for 150 ns;
   assert false report "end simulation" severity failure;
  end process;
end behavior; 

configuration CFG_LOG of test_dg is
 for behavior
      for logic_instance: digit_ext
      end for;
    end for;
     end CFG_LOG;

IEEE库；
使用IEEE.numeric_std.all；
使用IEEE.std_logic_1164.all；
图书馆工作；
使用work.pack1.all；
实体测试
终端实体；
测试单元dg的架构行为是
组件数字_ext为
一般的(
add_width:integer:=12；--节点地址的长度
深度：整数：=15）；
港口(
suc_add:in std_logic_vector（add_width-1 down to 0）；--源地址
des_add:in std_logic_vector（add_width-1 down to 0）；--目标地址
flg2：输出标准逻辑；
flg3：输出标准逻辑；
flg4：输出标准逻辑；
flg5：输出标准逻辑；
flg6：输出标准逻辑）；
端部元件；
信号sucadd\u t:std\u逻辑\u向量（11到0）：=“000000000000”；
信号消除：标准逻辑向量（11到0）：=“000000000000”；
开始
逻辑实例：数字外部端口映射（如添加、删除）；
来源地址：进程
开始
如添加到下一步：
获取文件：modelsim_tutorial.pdf和modelsim_quickref.pdf

完成本教程。编译包（pack1）。然后编译您的设计（数字扩展）和测试台（测试dg）。请注意，除非映射这些标志，否则您不会在测试台上看到它们。
听起来好像您没有编译设计。尝试先编译设计，然后编译测试台。
    use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
-- =============================================================================
library work;
use work.pack1.all;
-- =============================================================================
entity digit_ext is  
  generic (
    add_width : integer := 12;                                                     -- length of the adress of the node
    depth : integer := 15);
port (
  suc_add : in std_logic_vector(add_width-1 downto 0);                             -- source address
  des_add : in std_logic_vector(add_width-1 downto 0);                             -- destination address
  flg2 : out std_logic;
  flg3 : out std_logic;
  flg4 : out std_logic;
  flg5 : out std_logic;
  flg6 : out std_logic); 
end digit_ext;
-- =============================================================================
architecture behavior of digit_ext is
  type info is array (0 to depth) of integer;

      signal self_info: info := (500,4,0,0,3,0,0,2,0,1,1,2,0);
      signal equ_add : integer;
      signal i1: integer;
      signal i2: integer;
      signal i3: integer;
      signal flg1 : integer := 0;
      signal v1 : integer;
      signal v2 : std_logic := '0';
      signal v3 : std_logic := '0';
      signal v4 : std_logic := '0';
      signal v5 : std_logic := '0';
      signal v6 : std_logic := '0';
  begin
-- ============================================================================= 
      flg2 <= v2;                                                                 -- assignment of signal to the output ports 
      flg3 <= v3;   
      flg4 <= v4;
      flg5 <= v5;
      flg6 <= v6;
-- =============================================================================      
step1:process (des_add,equ_add,i1,i2,i3)                                          -- to convert bcd address of destination to integer and to split the digits
          begin
          bcd_conv(des_add,equ_add,i1,i2,i3);
          v1 <= (equ_add - self_info(1));                                         -- find distance between the current address and destination address
          if (v1 < 0) then
              flg1 <= 1;
              elsif (v1 > 0 ) then
                    flg1 <= 2;
              elsif (v1 = 0) then
                    flg1 <= 3;
          end if;
        end process;
-- =============================================================================
step2:process(flg1)                                                              -- process to find the up or down neighbour based on set value of flag
      begin
        if (flg1 = 1) then
            v2 <= compare (i1,i2,i3,self_info(2),self_info(3),self_info(4));
            v3 <= compare (i1,i2,i3,self_info(5),self_info(6),self_info(7));
            elsif (flg1 = 2) then
                  v4 <= compare (i1,i2,i3,self_info(8),self_info(9),self_info(10));
                  v5 <= compare (i1,i2,i3,self_info(11),self_info(12),self_info(13));
            elsif (flg1 = 3)then
                   v6 <= '1';
                   v2 <= '0';
                   v3 <= '0';
                   v4 <= '0';
                   v5 <= '0';
        end if;
      end process;
-- =============================================================================
end behavior;
-- =============================================================================