VHDL代码中的混淆

我正在尝试用VHDL实现32位乘法器的重新编码逻辑。此外，要重新编码的输入位向量（

x_in

）还有一个额外的输入“one”。其目的是当“一”是

'1'

时，输出应该是

x_in

，否则如果“一”是

'0'

，它应该是

x_in

的两倍。如果“负”很高，那么输出必须反转。以下是我的VHDL代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

package sum_vector_pkg is
    type partial_sum_array is array (0 to 15) of std_logic_vector(32 downto 0);
end package;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.sum_vector_pkg.all;
use work.test.all;

entity multipleGenerator is 
    generic(
           constant WIDTH : integer := 32
    );
    port(
        x_in      : in std_logic_vector(WIDTH - 1 downto 0);
        one       : in std_logic_vector(WIDTH/2 - 1 downto 0);
        multiple  : out partial_sum_array
    );
end entity multipleGenerator;

architecture logic of multipleGenerator is
    signal sum  : std_logic_vector(WIDTH downto 0);

begin
    gen : for i in 0 to WIDTH/2 - 1 generate
        process (one,sum,x_in) is begin
            case one(i) is
                when '0' => sum <= x_in & '0'; -- twice x_in
                when '1' => sum <= '0' & x_in; -- same as x_in
                when others => sum <= x"00000000" &'0';
            end case;
            multiple(i) <= sum;
            report "The sum is " & toString(sum) & " one(i) is " & toString(one(i)) & " x_in is " & toString(x_in);
        end process;
    end generate;
end architecture logic;

当我运行上述代码时，我在输出中得到

'X'

。以下是示例输出：

    Time: 200 ns  Iteration: 2  Region: /tb_multiplegenerator/u_mult/gen(12)
# ** Note: The sum is 0000000000000000000XX00XX00XX00XX one(i) is 0 x_in is 00000000000000000001000100010001
#    Time: 200 ns  Iteration: 2  Region: /tb_multiplegenerator/u_mult/gen(13)
# ** Note: The sum is 0000000000000000000XX00XX00XX00XX one(i) is 0 x_in is 00000000000000000001000100010001
#    Time: 200 ns  Iteration: 2  Region: /tb_multiplegenerator/u_mult/gen(14)
# ** Note: The sum is 0000000000000000000XX00XX00XX00XX one(i) is 0 x_in is 00000000000000000001000100010001
#    Time: 200 ns  Iteration: 2  Region: /tb_multiplegenerator/u_mult/gen(15)

---

有人能解释一下为什么这个代码不起作用吗？

问题已经出现在您的

multipleGenerator

实体中。您可以定义信号

sum

，并在

generate

语句中重复使用该信号。然而，这些赋值在VHDL中并行进行。因此，实际上，您正在为16个驱动程序分配

sum

但实际上你不需要求和

清理代码（并使其成为vhdl 2008）

标准\u逻辑\u向量\u向量\u包装.vhd：

library ieee;
use ieee.std_logic_1164.all;

package std_logic_vector_vector_pkg is
    type std_logic_vector_vector is array (natural range <>) of std_logic_vector;
end package;

multipleGenerator.vhd

library ieee;
use ieee.std_logic_1164.all;
use work.std_logic_vector_vector_pkg.all;
use work.converter_pkg.all;

entity multipleGenerator is 
    generic(
        WIDTH : integer := 32
    );
    port(
        x_in      : in std_logic_vector(WIDTH - 1 downto 0);
        one       : in std_logic_vector(WIDTH/2 - 1 downto 0);
        multiple  : out std_logic_vector_vector(0 to WIDTH/2 - 1)(WIDTH downto 0)
    );
end entity;

architecture rtl of multipleGenerator is
begin
    gen : for i in 0 to WIDTH/2 - 1 generate
        multiple(i) <= '0' & x_in when one(i)='1' else x_in & '0';
    end generate;

    process(one)
    begin
        for i in 0 to WIDTH/2 - 1 loop 
            report "The sum is " & to_string(multiple(i)) &
                " one(" & integer'image(i) & ") is " & std_logic'image(one(i)) &
                " x_in is " & to_string(x_in);
        end loop;
    end process;
end architecture;

ieee库；
使用ieee.std_logic_1164.all；
使用work.std\u logic\u vector\u vector\u pkg.all；
使用work.converter_pkg.all；
实体多重生成器是
一般的(
宽度：整数：=32
);
港口(
x_in:in标准逻辑向量（宽度-1到0）；
一：标准逻辑向量（宽度/2-1到0）；
多：输出标准逻辑向量向量向量（0至宽度/2-1）（宽度降至0）
);
终端实体；
介绍了多机rtl的体系结构
开始
gen:对于0中的i，宽度为/2-1生成
多（i）a怎么样？您可以使用函数bv_negate模拟包mlite_pack，并提供一个测试台。至少在发生故障时为1和neg提供一个清晰的值，并显示这些报告语句是如何生成的。您提供的内容无法复制您的问题。@user1155120我已经更新了问题并提供了测试台，请看一看，它现在应该可以复制了。您的代码中生成的“总和是…”输出在哪里？我有一个单独的包，我没有包含它以使问题可读。但是从波形上看，输出应该是明显的。但如果需要，我可以添加。尝试删除
std\u logic\u arith
和
std\u logic\u unsigned
，可能它们以意外的方式干扰了正常的
std\u logic\u vector
。
library ieee;
use ieee.std_logic_1164.all;

package std_logic_vector_vector_pkg is
    type std_logic_vector_vector is array (natural range <>) of std_logic_vector;
end package;

library ieee;
use ieee.std_logic_1164.all;

package converter_pkg is
    function to_string(slv : std_logic_vector) return string;
end package;

package body converter_pkg is
    function to_string(slv : std_logic_vector) return string is
        variable output : string(1 to slv'length) := (others => 'X');
        variable i_o : positive := 1;
    begin
        for i_s in slv'high downto slv'low loop
            output(i_o) := std_logic'image(slv(i_s))(2);
            i_o := i_o + 1;
        end loop;
        return output;
    end function;
end package body;

library ieee;
use ieee.std_logic_1164.all;
use work.std_logic_vector_vector_pkg.all;
use work.converter_pkg.all;

entity multipleGenerator is 
    generic(
        WIDTH : integer := 32
    );
    port(
        x_in      : in std_logic_vector(WIDTH - 1 downto 0);
        one       : in std_logic_vector(WIDTH/2 - 1 downto 0);
        multiple  : out std_logic_vector_vector(0 to WIDTH/2 - 1)(WIDTH downto 0)
    );
end entity;

architecture rtl of multipleGenerator is
begin
    gen : for i in 0 to WIDTH/2 - 1 generate
        multiple(i) <= '0' & x_in when one(i)='1' else x_in & '0';
    end generate;

    process(one)
    begin
        for i in 0 to WIDTH/2 - 1 loop 
            report "The sum is " & to_string(multiple(i)) &
                " one(" & integer'image(i) & ") is " & std_logic'image(one(i)) &
                " x_in is " & to_string(x_in);
        end loop;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use work.std_logic_vector_vector_pkg.all;

entity multipleGenerator_tb is end entity;

architecture behavioral of multipleGenerator_tb is
    signal b        : std_logic_vector(31 downto 0);
    signal one      : std_logic_vector(15 downto 0);
    signal multiple : std_logic_vector_vector(0 to one'length-1)(x'length downto 0);
begin
    process
    begin
        x <= (others => '0');
        one <= (others => '0');
        wait for 200 ns;
        x <= x"00001111";
        one <= x"0011";
        wait;
    end process;

    u_mult: entity work.multipleGenerator
        generic map (
            WIDTH => x'length
        )
        port map (
            x_in     => x,   
            one      => one,
            multiple => multiple
        );
end architecture;