Vhdl 十六进制到7段编码器语法错误，带有When stations
我正在尝试创建一个十六进制到7段的编码器。当我进行综合时，我在每一行中都会出现错误，其中有一个When语句，我不知道为什么。如果有人能给我指出正确的方向，我将非常感激Vhdl 十六进制到7段编码器语法错误，带有When stations,vhdl,Vhdl,我正在尝试创建一个十六进制到7段的编码器。当我进行综合时，我在每一行中都会出现错误，其中有一个When语句，我不知道为什么。如果有人能给我指出正确的方向，我将非常感激 architecture Behavioral of encoder is begin CASE hex IS WHEN "0000" => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '1'; f
architecture Behavioral of encoder is
begin
CASE hex IS
WHEN "0000" =>
a <= '1';
b <= '1';
c <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '0';
...
a不能在流程之外使用案例结构 如果你想要一个案例结构，你可以写：
process (hex)
begin
CASE hex IS
WHEN "0000" =>
a <= '1';
b <= '1';
c <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '0';
WHEN ...
WHEN ...
WHEN others =>
a <= '0'
b <= '0'
etc...
end process
bcd <= "0000000" when hex = "0000" else
"0011010" when hex = "0001" else
...
"0011110" when hex = "0010" else
"0000000"
a <= sevseg(0)
b <= sevseg(1)
c <= sevseg(2)
d <= sevseg(2)
...
bcd您不能在流程之外使用案例结构
如果你想要一个案例结构，你可以写：
process (hex)
begin
CASE hex IS
WHEN "0000" =>
a <= '1';
b <= '1';
c <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '0';
WHEN ...
WHEN ...
WHEN others =>
a <= '0'
b <= '0'
etc...
end process
在rtl部分：
bcd <= "0000000" when hex = "0000" else
"0011010" when hex = "0001" else
...
"0011110" when hex = "0010" else
"0000000"
a <= sevseg(0)
b <= sevseg(1)
c <= sevseg(2)
d <= sevseg(2)
...
bcd您不能在流程之外使用案例结构
如果你想要一个案例结构，你可以写：
process (hex)
begin
CASE hex IS
WHEN "0000" =>
a <= '1';
b <= '1';
c <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '0';
WHEN ...
WHEN ...
WHEN others =>
a <= '0'
b <= '0'
etc...
end process
在rtl部分：
bcd <= "0000000" when hex = "0000" else
"0011010" when hex = "0001" else
...
"0011110" when hex = "0010" else
"0000000"
a <= sevseg(0)
b <= sevseg(1)
c <= sevseg(2)
d <= sevseg(2)
...
bcd您不能在流程之外使用案例结构
如果你想要一个案例结构，你可以写：
process (hex)
begin
CASE hex IS
WHEN "0000" =>
a <= '1';
b <= '1';
c <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '0';
WHEN ...
WHEN ...
WHEN others =>
a <= '0'
b <= '0'
etc...
end process
在rtl部分：
bcd <= "0000000" when hex = "0000" else
"0011010" when hex = "0001" else
...
"0011110" when hex = "0010" else
"0000000"
a <= sevseg(0)
b <= sevseg(1)
c <= sevseg(2)
d <= sevseg(2)
...
bcd除了anderswb答案外，还需了解完整性：
这里还声明了一个子程序，在本例中是一个函数，并在此处显示为实体声明项，其中可由该实体的任何体系结构使用：
library ieee;
use ieee.std_logic_1164.all;
entity hex_7seg is
port (
clk: in std_logic;
val: in std_logic_vector (31 downto 0);
anode: out std_logic_vector (7 downto 0);
segment: out std_logic_vector (6 downto 0)
);
-- seven segment display
--
-- a
-- f b
-- g
-- e c
-- d
--
-- SEGMENT is defined (g downto a)
--
function HEX_TO_7SEG (bcd: std_logic_vector(3 downto 0))
return std_logic_vector is
begin
case bcd is
when "0000" => return "1000000"; -- 0
when "0001" => return "1111001"; -- 1
when "0010" => return "0100100"; -- 2
when "0011" => return "0110000"; -- 3
when "0100" => return "0011001"; -- 4
when "0101" => return "0010010"; -- 5
when "0110" => return "0000010"; -- 6
when "0111" => return "1111000"; -- 7
when "1000" => return "0000000"; -- 8
when "1001" => return "0011000"; -- 9
when "1010" => return "0001000"; -- A
when "1011" => return "0000011"; -- b
when "1100" => return "0111001"; -- C
when "1101" => return "0100001"; -- d
when "1110" => return "0000110"; -- E
when "1111" => return "0001110"; -- F
when others => return "XXXXXXX"; -- does not synthesize
end case;
end function;
end entity;
还可以使用带有十六进制值的ROM作为索引：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hex_7seg is
port (
clk: in std_logic;
val: in std_logic_vector (31 downto 0);
anode: out std_logic_vector (7 downto 0);
segment: out std_logic_vector (6 downto 0)
);
-- seven segment display
--
-- a
-- f b
-- g
-- e c
-- d
--
-- SEGMENT is defined (g downto a)
--
type segment7 is array (integer range 0 to 15) of
std_logic_vector (6 downto 0);
constant hex_to_segment: segment7 := (
"1000000", -- 0
"1111001", -- 1
"0100100", -- 2
"0110000", -- 3
"0011001", -- 4
"0010010", -- 5
"0000010", -- 6
"1111000", -- 7
"0000000", -- 8
"0011000", -- 9
"0001000", -- A
"0000011", -- b
"0111001", -- C
"0100001", -- d
"0000110", -- E
"0001110" -- F
);
end entity;
architecture foo of hex_7seg is
signal seg7_val: integer range 0 to 15;
signal hex: std_logic_vector (3 downto 0);
begin
seg7_val <= to_integer(unsigned(hex));
segment <= hex_to_segment(seg7_val);
end architecture;
ieee库；
使用ieee.std_logic_1164.all；
使用ieee.numeric_std.all；
实体hex_7seg为
港口（
clk：标准逻辑中；
val：标准逻辑向量（31到0）；
阳极：输出标准逻辑向量（7到0）；
段：输出标准逻辑向量（6到0）
);
--七段显示
--
--a
--f-b
--g
--电子商务
--d
--
--定义了段（从g到a）
--
segment7类型是数组（整数范围0到15）
标准逻辑向量（6到0）；
恒定十六进制至段：段7:=(
"1000000", -- 0
"1111001", -- 1
"0100100", -- 2
"0110000", -- 3
"0011001", -- 4
"0010010", -- 5
"0000010", -- 6
"1111000", -- 7
"0000000", -- 8
"0011000", -- 9
“0001000”
“0000011”--b
“01111001”，--C
“0100001”，--d
“0000110”--E
“0001110”-F
);
终端实体；
hex_7seg的架构是
信号seg7_val：整数范围0至15；
信号十六进制：标准逻辑向量（3到0）；
开始
seg7_val除了anderswb答案外，完整性：
这里还声明了一个子程序，在本例中是一个函数，并在此处显示为实体声明项，其中可由该实体的任何体系结构使用：
library ieee;
use ieee.std_logic_1164.all;
entity hex_7seg is
port (
clk: in std_logic;
val: in std_logic_vector (31 downto 0);
anode: out std_logic_vector (7 downto 0);
segment: out std_logic_vector (6 downto 0)
);
-- seven segment display
--
-- a
-- f b
-- g
-- e c
-- d
--
-- SEGMENT is defined (g downto a)
--
function HEX_TO_7SEG (bcd: std_logic_vector(3 downto 0))
return std_logic_vector is
begin
case bcd is
when "0000" => return "1000000"; -- 0
when "0001" => return "1111001"; -- 1
when "0010" => return "0100100"; -- 2
when "0011" => return "0110000"; -- 3
when "0100" => return "0011001"; -- 4
when "0101" => return "0010010"; -- 5
when "0110" => return "0000010"; -- 6
when "0111" => return "1111000"; -- 7
when "1000" => return "0000000"; -- 8
when "1001" => return "0011000"; -- 9
when "1010" => return "0001000"; -- A
when "1011" => return "0000011"; -- b
when "1100" => return "0111001"; -- C
when "1101" => return "0100001"; -- d
when "1110" => return "0000110"; -- E
when "1111" => return "0001110"; -- F
when others => return "XXXXXXX"; -- does not synthesize
end case;
end function;
end entity;
还可以使用带有十六进制值的ROM作为索引：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hex_7seg is
port (
clk: in std_logic;
val: in std_logic_vector (31 downto 0);
anode: out std_logic_vector (7 downto 0);
segment: out std_logic_vector (6 downto 0)
);
-- seven segment display
--
-- a
-- f b
-- g
-- e c
-- d
--
-- SEGMENT is defined (g downto a)
--
type segment7 is array (integer range 0 to 15) of
std_logic_vector (6 downto 0);
constant hex_to_segment: segment7 := (
"1000000", -- 0
"1111001", -- 1
"0100100", -- 2
"0110000", -- 3
"0011001", -- 4
"0010010", -- 5
"0000010", -- 6
"1111000", -- 7
"0000000", -- 8
"0011000", -- 9
"0001000", -- A
"0000011", -- b
"0111001", -- C
"0100001", -- d
"0000110", -- E
"0001110" -- F
);
end entity;
architecture foo of hex_7seg is
signal seg7_val: integer range 0 to 15;
signal hex: std_logic_vector (3 downto 0);
begin
seg7_val <= to_integer(unsigned(hex));
segment <= hex_to_segment(seg7_val);
end architecture;
ieee库；
使用ieee.std_logic_1164.all；
使用ieee.numeric_std.all；
实体hex_7seg为
港口（
clk：标准逻辑中；
val：标准逻辑向量（31到0）；
阳极：输出标准逻辑向量（7到0）；
段：输出标准逻辑向量（6到0）
);
--七段显示
--
--a
--f-b
--g
--电子商务
--d
--
--定义了段（从g到a）
--
segment7类型是数组（整数范围0到15）
标准逻辑向量（6到0）；
恒定十六进制至段：段7:=(
"1000000", -- 0
"1111001", -- 1
"0100100", -- 2
"0110000", -- 3
"0011001", -- 4
"0010010", -- 5
"0000010", -- 6
"1111000", -- 7
"0000000", -- 8
"0011000", -- 9
“0001000”
“0000011”--b
“01111001”，--C
“0100001”，--d
“0000110”--E
“0001110”-F
);
终端实体；
hex_7seg的架构是
信号seg7_val：整数范围0至15；
信号十六进制：标准逻辑向量（3到0）；
开始
seg7_val除了anderswb答案外，完整性：
这里还声明了一个子程序，在本例中是一个函数，并在此处显示为实体声明项，其中可由该实体的任何体系结构使用：
library ieee;
use ieee.std_logic_1164.all;
entity hex_7seg is
port (
clk: in std_logic;
val: in std_logic_vector (31 downto 0);
anode: out std_logic_vector (7 downto 0);
segment: out std_logic_vector (6 downto 0)
);
-- seven segment display
--
-- a
-- f b
-- g
-- e c
-- d
--
-- SEGMENT is defined (g downto a)
--
function HEX_TO_7SEG (bcd: std_logic_vector(3 downto 0))
return std_logic_vector is
begin
case bcd is
when "0000" => return "1000000"; -- 0
when "0001" => return "1111001"; -- 1
when "0010" => return "0100100"; -- 2
when "0011" => return "0110000"; -- 3
when "0100" => return "0011001"; -- 4
when "0101" => return "0010010"; -- 5
when "0110" => return "0000010"; -- 6
when "0111" => return "1111000"; -- 7
when "1000" => return "0000000"; -- 8
when "1001" => return "0011000"; -- 9
when "1010" => return "0001000"; -- A
when "1011" => return "0000011"; -- b
when "1100" => return "0111001"; -- C
when "1101" => return "0100001"; -- d
when "1110" => return "0000110"; -- E
when "1111" => return "0001110"; -- F
when others => return "XXXXXXX"; -- does not synthesize
end case;
end function;
end entity;
还可以使用带有十六进制值的ROM作为索引：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hex_7seg is
port (
clk: in std_logic;
val: in std_logic_vector (31 downto 0);
anode: out std_logic_vector (7 downto 0);
segment: out std_logic_vector (6 downto 0)
);
-- seven segment display
--
-- a
-- f b
-- g
-- e c
-- d
--
-- SEGMENT is defined (g downto a)
--
type segment7 is array (integer range 0 to 15) of
std_logic_vector (6 downto 0);
constant hex_to_segment: segment7 := (
"1000000", -- 0
"1111001", -- 1
"0100100", -- 2
"0110000", -- 3
"0011001", -- 4
"0010010", -- 5
"0000010", -- 6
"1111000", -- 7
"0000000", -- 8
"0011000", -- 9
"0001000", -- A
"0000011", -- b
"0111001", -- C
"0100001", -- d
"0000110", -- E
"0001110" -- F
);
end entity;
architecture foo of hex_7seg is
signal seg7_val: integer range 0 to 15;
signal hex: std_logic_vector (3 downto 0);
begin
seg7_val <= to_integer(unsigned(hex));
segment <= hex_to_segment(seg7_val);
end architecture;
ieee库；
使用ieee.std_logic_1164.all；
使用ieee.numeric_std.all；
实体hex_7seg为
港口（
clk：标准逻辑中；
val：标准逻辑向量（31到0）；
阳极：输出标准逻辑向量（7到0）；
段：输出标准逻辑向量（6到0）
);
--七段显示
--
--a
--f-b
--g
--电子商务
--d
--
--定义了段（从g到a）
--
segment7类型是数组（整数范围0到15）
标准逻辑向量（6到0）；
恒定十六进制至段：段7:=(
"1000000", -- 0
"1111001", -- 1
"0100100", -- 2
"0110000", -- 3
"0011001", -- 4
"0010010", -- 5
"0000010", -- 6
"1111000", -- 7
"0000000", -- 8
"0011000", -- 9
“0001000”
“0000011”--b
“01111001”，--C
“0100001”，--d
“0000110”--E
“0001110”-F
);
终端实体；
hex_7seg的架构是
信号seg7_val：整数范围0至15；
信号十六进制：标准逻辑向量（3到0）；
开始
seg7_val除了anderswb答案外，完整性：
在本例中，还声明了一个子程序