Arrays VHDL将整数索引向量分配给枚举索引向量

有人知道这在VHDL中是否合法吗

type foo is (ONE, TWO, THREE);
signal fooArray is array (foo'left to foo'right) of int;
signal intArray is array (0 to 2) of int;

fooArray <= intArray;   -- is this statement legal?

类型foo为（一、二、三）；
信号fooArray是int的数组（foo'左到foo'右）；
信号intArray是int的数组（0到2）；
fooArray问题在于您的代码片段不代表合法的VHDL

这三种尝试构成了一种叙述：

entity eiv is
end entity;

architecture foo of eiv is

    type foo is (ONE, TWO, THREE);
    signal fooArray is array (foo'left to foo'right) of int;
    signal intArray is array (0 to 2) of int;

begin

Statement:
    fooArray <= intArray;   -- is this statement legal?

end architecture;

简言之，答案是否定的，该声明不合法。Type
foo
不是整数子类型，这使得
FooArrayType
与
intarrarytype
不兼容

通知

fooArray <= fooArrayType(intArray);

不那么复杂：
类型fooArray是int的数组（foo）fooArray我必须为这种糟糕的vhdl编码道歉。我编辑了我的主要问题，试图澄清我想找出的问题。我想知道是否可以将枚举索引的数组分配给整数索引的相同大小的数组。我希望我的新代码能让这一点更清楚，希望你能回答这个问题。
entity eiv is
end entity;

architecture foo of eiv is

    type foo is (ONE, TWO, THREE);
    type int_array is array (natural range <>) of integer;
    signal fooArray: int_array (foo'left to foo'right);
    signal intArray: int_array (0 to 2);

begin

Statement:
    fooArray <= intArray;   -- is this statement legal?

end architecture;

entity eiv is
end entity;

architecture foo of eiv is

    type foo is (ONE, TWO, THREE);
    type int_array is array (natural range <>) of integer;
    signal fooArray: int_array (foo'POS(ONE) to foo'POS(THREE));
    signal intArray: int_array (0 to 2);

begin

Statement:
    fooArray <= intArray;   -- is this statement legal?

end architecture;

entity eiv is
end entity;

architecture fooArch of eiv is

    type foo is (ONE, TWO, THREE);
    type fooArrayType is array(foo) of integer;
    type intArrayType is array(0 to 2) of integer;

    signal fooArray : fooArrayType;
    signal intArray : intArrayType;

begin

Statement:
    fooArray <= intArray;   -- is this statement legal?

end architecture;

fooArray <= fooArrayType(intArray);

entity eiv1 is
end entity;

architecture fooArch of eiv1 is

    type foo is (ONE, TWO, THREE);
    type fooArrayType is array(foo) of integer;
    type intArrayType is array(0 to 2) of integer;

    signal fooArray : fooArrayType;
    signal intArray : intArrayType;

    function conv_fooarray (v: intArrayType) return fooArrayType is
        variable temp:  fooArrayType;
    begin
        for i in v'range loop
            temp(foo'VAL(i))  := v(i);
        end loop;
        return temp;
    end function;

begin
Statement:
    fooArray <= conv_fooarray(intArray);   -- this statement is legal

end architecture;