Buffer 使用BUFG驱动时钟负载
我正在尝试处理输出到DVI芯片的像素数据。由于DVI芯片寄存器使用来自时钟分频器的I2C(因此需要<500 KHz的时钟)进行编程,因此使用了多种时钟频率 DVI芯片需要一个40 MHz的差分像素时钟,然而,DVI每两个周期显示半个字节,因此每半个周期需要另一个80 MHz时钟将每半个像素推送到数据线上,这些都来自DCM 这导致了各种各样的问题。我试图仅使用双像素时钟速率交换每一半像素,但我得到了错误:Buffer 使用BUFG驱动时钟负载,buffer,vhdl,clock,xilinx-ise,spartan,Buffer,Vhdl,Clock,Xilinx Ise,Spartan,我正在尝试处理输出到DVI芯片的像素数据。由于DVI芯片寄存器使用来自时钟分频器的I2C(因此需要'0'); HSYNC,VSYNC:OUT STD_逻辑:='1'; 启用:输出标准_逻辑:=“0”); 终端组件DVI_接口; 组件DVI_多路复用器 端口(PXLCLK:标准逻辑中; PXLCLK2X:标准逻辑中; PXL_DAT:标准逻辑向量(23向下至0);--像素为RGB 数据:输出标准逻辑向量(11到0);--多路输出 复位(N:标准逻辑中)--复位低信号 终端组件DVI_MUX; --
此设计包含一个全局缓冲区实例,
驱动网络,即驱动以下(前30个)
非时钟负载引脚。
因此,我在DCM的输出和使用该信号的组件之间添加了一个BUFG元素,但它没有改变任何东西,相反,错误现在在BUFG的输入和输出上抛出了两次
- 我该如何解决这个问题?因为我刚刚添加了一个BUFG,它不喜欢它李>
ieee库;
使用ieee.std_logic_1164.ALL;
使用ieee.numeric_std.ALL;
UNISIM图书馆;
使用UNISIM.VComponents.all;
实体I2CBus是
港口(
SYSCLK\u N:标准逻辑中——系统200MHz差分时钟
SYSCLK\u P:标准逻辑中;
BTN:在标准逻辑中;--手动更改重置
LED:输出标准逻辑向量(3到0);--观察复位值
SCL_DBG:OUT STD_逻辑;--将SCL复制到输出引脚
SDA_DBG:OUT STD_LOGIC;--将SDA复制到输出引脚
SCL:OUT STD_逻辑——串行时钟线
SDA:INOUT标准_逻辑;--串行数据线
DVIRESET\u N:OUT STD\u LOGIC;--重置为dvi设备
DVI_启用:OUT STD_逻辑;--启用DVI设备输入(高电平)
PXLCLK_P:OUT STD_LOGIC;--通过缓冲区的像素时钟差分对
PXLCLK\u N:输出标准逻辑;
DVI_数据:输出STD_逻辑_向量(11到0);--12位多路复用像素到DVI
HSYNC:OUT STD_LOGIC;--水平/垂直同步定时脉冲
输出标准逻辑
);
终端I2C总线;
I2CBus的架构行为是
组件IIC_MASTER——以I2C协议发送数据写入SDA总线
端口(SCL:STD_逻辑中;
SCL2X:标准逻辑中;
复位N:在标准逻辑中;
ENA:标准逻辑;
ADR:标准逻辑向量(6到0);
REG:标准逻辑向量(7到0);
RW:标准逻辑中;
DAT_WR:标准逻辑向量(7到0);
忙:输出标准逻辑;
SDA:INOUT标准逻辑;
确认错误:缓冲区标准逻辑);
终端组件IIC_主控器;
组件DCM——获取输入系统差分时钟,生成更多时钟
港口(
SYSCLK_P:IN STD_LOGIC;--端口200MHZ差分时钟
SYSCLK\u N:标准逻辑中;
--时钟输出端口
SYSCLK:输出标准逻辑;
PXLCLK:输出标准逻辑;
PXLCLK2X:输出标准_逻辑
);
端部元件;
组件时钟分频器——将系统时钟向下分为i2c总线时钟线
通用(输入频率:整数;
OUT1_FREQ:整数;
输出2_频率:整数);
端口(SYSCLK:标准逻辑中;
复位N:在标准逻辑中;
复位输出:输出标准逻辑;
OUT1:OUT标准逻辑;
OUT2:OUT标准逻辑);
端部组件CLK_分配器;
组件DVI_初始化——将CH7301c寄存器初始化为必要的操作值
端口(SYSCLK:标准逻辑中;
确认错误:在标准逻辑中;
忙:在标准逻辑中;
复位N:在标准逻辑中;
计数:输出标准逻辑向量(3到0);
DVI_WR:OUT标准_逻辑:='0';
DVI_REGDATA:输出标准逻辑向量(7到0);
DVI_WDATA:OUT标准逻辑向量(7到0);
终端组件DVI_初始化;
组件DVI_接口——输出同步脉冲,控制启用和管理像素地址
端口(像素时钟:标准逻辑中;
复位N:在标准逻辑中;
PXL_ADDR:OUT标准逻辑向量(19到0):=(其他=>'0');
HSYNC,VSYNC:OUT STD_逻辑:='1';
启用:输出标准_逻辑:=“0”);
终端组件DVI_接口;
组件DVI_多路复用器
端口(PXLCLK:标准逻辑中;
PXLCLK2X:标准逻辑中;
PXL_DAT:标准逻辑向量(23向下至0);--像素为RGB
数据:输出标准逻辑向量(11到0);--多路输出
复位(N:标准逻辑中)--复位低信号
终端组件DVI_MUX;
--投入
信号复位输入:标准逻辑;——输入复位按钮
----输出------
信号sda\U内部:标准逻辑;——内部SDA
----时钟-----
信号SCL\U内部:标准逻辑;——i2c时钟
信号SCL2X_内部:标准_逻辑;——i2c x2用于加载SDA数据
信号系统时钟:标准逻辑--系统时钟
信号pxlclk_p_int:std_逻辑--差分像素时钟对
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.VComponents.all;
ENTITY I2CBus IS
PORT(
SYSCLK_N : IN STD_LOGIC; --system 200MHz differential clock
SYSCLK_P : IN STD_LOGIC;
BTN : IN STD_LOGIC; -- to manually change reset
LED : OUT STD_LOGIC_VECTOR(3 downto 0); --to observe reset value
SCL_DBG : OUT STD_LOGIC; -- copy of SCL to output pin
SDA_DBG : OUT STD_LOGIC; --copy of SDA to output pin
SCL : OUT STD_LOGIC; --Serial Clock Line
SDA : INOUT STD_LOGIC; --Serial Data Line
DVIRESET_N : OUT STD_LOGIC; --reset_n to dvi device
DVI_ENABLE : OUT STD_LOGIC; --enable DVI device inputs (active high)
PXLCLK_P : OUT STD_LOGIC; --pixel clock differential pair through buffers
PXLCLK_N : OUT STD_LOGIC;
DVI_DATA : OUT STD_LOGIC_VECTOR(11 downto 0); --12 bit multiplexed pixel to DVI
HSYNC : OUT STD_LOGIC; --Horizontal/Vertical sync timing pulses
VSYNC : OUT STD_LOGIC
);
END I2CBus;
ARCHITECTURE behavior OF I2CBus IS
COMPONENT IIC_MASTER --sends data to write out onto SDA bus line in I2C protocol
PORT(SCL : IN STD_LOGIC;
SCL2X : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENA : IN STD_LOGIC;
ADR : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
REG : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RW : IN STD_LOGIC;
DAT_WR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
BUSY : OUT STD_LOGIC;
SDA : INOUT STD_LOGIC;
ACK_ERR : BUFFER STD_LOGIC);
END COMPONENT IIC_MASTER;
COMPONENT DCM --takes input system differential clocks, generates further clocks
PORT(
SYSCLK_P : IN STD_LOGIC; -- CLOCK IN PORTS 200MHZ DIFFERENTIAL
SYSCLK_N : IN STD_LOGIC;
-- CLOCK OUT PORTS
SYSCLK : OUT STD_LOGIC;
PXLCLK : OUT STD_LOGIC;
PXLCLK2X : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT CLK_DIVIDER --divides system clock down for i2c bus clock line
GENERIC(INPUT_FREQ : INTEGER;
OUT1_FREQ : INTEGER;
OUT2_FREQ : INTEGER);
PORT(SYSCLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
RESET_N_OUT : OUT STD_LOGIC;
OUT1 : OUT STD_LOGIC;
OUT2 : OUT STD_LOGIC);
END COMPONENT CLK_DIVIDER;
COMPONENT DVI_INITIALISE --initialises CH7301c registers to necessary operation values
PORT(SYSCLK : IN STD_LOGIC;
ACK_ERR : IN STD_LOGIC;
BUSY : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
COUNT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DVI_WR : OUT STD_LOGIC := '0';
DVI_REGDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
DVI_WDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT DVI_INITIALISE;
COMPONENT DVI_INTERFACE --outputs sync pulses, controls enable and manages pixel addresses
PORT(PIXEL_CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
PXL_ADDR : OUT STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
HSYNC, VSYNC : OUT STD_LOGIC := '1';
ENABLE : OUT STD_LOGIC := '0');
END COMPONENT DVI_INTERFACE;
COMPONENT DVI_MUX
PORT(PXLCLK : IN STD_LOGIC;
PXLCLK2X : IN STD_LOGIC;
PXL_DAT : IN STD_LOGIC_VECTOR(23 DOWNTO 0); --pixel as RGB
DATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --multiplexed output
RESET_N : IN STD_LOGIC); --reset low signal
END COMPONENT DVI_MUX;
--Inputs
signal reset_n_input : std_logic; -- input reset from button
----Outputs ------
signal sda_internal : STD_LOGIC; -- Internal SDA
----Clocks-----
signal SCL_internal : std_logic; -- i2c clock
signal SCL2X_internal : std_logic; -- i2c x2 to load SDA data
signal sysclk : std_logic; --system clock
signal pxlclk_p_int : std_logic; --differential pixel clock pair
signal pxlclk_n_int : std_logic;
signal pxlclk : std_logic; --pxlclk after BUFG
signal pxlclk2x_int : STD_LOGIC; --2x pixel clock for loading pixel data
-----Internal Control Signals ---
signal reset_n : std_logic; --active high
signal busy : std_logic; --low when not i2c not busy
signal ack_err : std_logic; --high when i2c ackknowledge error occurs
----Internal Data-----
signal i2c_reg : STD_LOGIC_VECTOR(7 DOWNTO 0); --register data for I2C
signal i2c_rw : STD_LOGIC; --R/W* for I2C
signal i2c_data : STD_LOGIC_VECTOR(7 DOWNTO 0); --Data for I2C
BEGIN
master : IIC_Master
port map(
SCL => SCL_internal,
SCL2X => SCL2X_internal,
RESET_N => RESET_N,
ENA => '1',
ADR => "1110110",
REG => i2c_reg,
RW => i2c_rw,
DAT_WR => i2c_data,
BUSY => busy,
SDA => sda_internal,
ACK_ERR => ack_err
);
DCM_SYS : DCM
port map(
SYSCLK_P => SYSCLK_P, --take differential input clock
SYSCLK_N => SYSCLK_N,
SYSCLK => sysclk, --200 MHz system clock
PXLCLK => pxlclk, --and pixel clock
PXLCLK2X => pxlclk2x_int --pixel clock at double rate
);
Clk_Div : Clk_Divider
generic map(
INPUT_FREQ => 200000000, --200 MHz system input
OUT1_FREQ => 100000, --to work correctly, 200 must go into all frequencies (x2).
OUT2_FREQ => 200000 --i.e. from 200, cannot generate 40 as 200/40/2 = 2.5, which will be 2
)
port map(
SYSCLK => sysclk,
RESET_N => reset_n_input,
RESET_N_OUT => reset_n,
OUT1 => scl_internal,
OUT2 => scl2x_internal
);
data_load : component DVI_INITIALISE
port map(
SYSCLK => sysclk,
ACK_ERR => ack_err,
BUSY => busy,
RESET_N => reset_n,
COUNT => LED,
DVI_WR => i2c_rw,
DVI_REGDATA => i2c_reg,
DVI_WDATA => i2c_data
);
interface : DVI_INTERFACE
port map(
PIXEL_CLK => pxlclk_p_int,
RESET_N => reset_n,
PXL_ADDR => open,
HSYNC => HSYNC,
VSYNC => VSYNC,
ENABLE => DVI_ENABLE
);
pxl_mux : DVI_MUX
port map(
PXLCLK => pxlclk_p_int,
PXLCLK2X => pxlclk2x_int,
PXL_DAT => x"FF0000",
DATA => DVI_DATA,
RESET_N => reset_n
);
------------OUTPUT BUFFERS (CLOCK FORWARDING)------------
ODDR_pxlclk_p : ODDR2
generic map(
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => PXLCLK_P, --output to positive output
C0 => pxlclk_p_int, --differential input
C1 => pxlclk_n_int,
CE => '1', --chip enable tied high
D0 => '1',
D1 => '0',
R => '0',
S => '0'
);
ODDR_pxlclk_n : ODDR2
generic map(
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => PXLCLK_N, --output to negative output
C0 => pxlclk_n_int,
C1 => pxlclk_p_int,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0'
);
out2_bufg : BUFG port map(I => pxlclk, O => pxlclk_p_int); --ERROR THROWN ON I/O HERE
----------------Mappings---------------------------
reset_n_input <= not BTN; --when button pressed, reset
SCL <= 'Z' when scl_internal = '1' else scl_internal;
SCL_DBG <= 'Z' when scl_internal = '1' else scl_internal;
SDA <= sda_internal;
SDA_DBG <= SDA; --copy SDA to debug line
DVIRESET_N <= reset_n; --reset DVI device
pxlclk_n_int <= not pxlclk_p_int; --create differential pair
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY DVI_MUX IS
PORT(
PXLCLK : IN STD_LOGIC; --pixel clock
PXLCLK2X : IN STD_LOGIC; --double freq. pixel clock
PXL_DAT : IN STD_LOGIC_VECTOR(23 downto 0); --pixel in RGB format
DATA : OUT STD_LOGIC_VECTOR(11 downto 0); --
RESET_N : IN STD_LOGIC
);
END ENTITY DVI_MUX;
architecture RTL of DVI_Mux is
begin
mux_proc : process(PXLCLK2X)
begin
if falling_edge(PXLCLK2X) then
if PXLCLK = '0' then -- if pxlclk low, load first half of pixel
DATA <= PXL_DAT(23 downto 16) & PXL_DAT(11 downto 8);
else --else load second half
DATA <= PXL_DAT(15 downto 12) & PXL_DAT(7 downto 0);
end if;
if RESET_N = '0' then --if reset active7
DATA <= (others => '1');
end if;
end if;
end process;
end architecture RTL;
pxclk_inverted <= not pxlclk;
ODDR_pxlclk_p : ODDR2
generic map(
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => PXLCLK_OUT,
C0 => pxlclk,
C1 => pxclk_inverted,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0'
);
inst_obufds : OBUFDS
generic map (
IOSTANDARD=>"LVDS_25"
)
port map
(
O => PXLCLK_OUT_P,
OB => PXLCLK_OUT_N,
I => PXLCLK_OUT
);
inst_obufds : OBUFDS
generic map ( IOSTANDARD=>"LVDS_25" )
port map
( O => DIFF_P,
OB => DIFF_N,
I => internal_signal
);