Mealy机器1011检测器的VHDL实现

我为Mealy machine编写了一个VHDL程序，可以检测模式1011，如下所示：

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mealy_detector_1011 IS
    PORT(
        rst_n   : IN STD_LOGIC;
        clk     : IN STD_LOGIC;
        data    : IN STD_LOGIC;
        result  : OUT STD_LOGIC);
END ENTITY;

ARCHITECTURE beh OF mealy_detector_1011 IS
    TYPE state IS (IDLE, GOT1, GOT10, GOT101);
    SIGNAL current_state : state;
    SIGNAL next_state   : state;
BEGIN
    REG: PROCESS(clk, rst_n)
    BEGIN
        IF rst_n = '0' THEN
            current_state <= IDLE;
        ELSIF rising_edge(clk) THEN
            current_state <= next_state;
        END IF;
    END PROCESS REG;

    NEXTSTATE: PROCESS(data, current_state)
    BEGIN
        CASE current_state IS
            WHEN IDLE =>
                IF data = '1' THEN
                    next_state <= GOT1;
                ELSE next_state <= IDLE;
                END IF;
            WHEN GOT1 =>
                IF data = '0' THEN
                    next_state <= GOT10;
                ELSE next_state <= GOT1;
                END IF;
            WHEN GOT10 =>
                IF data = '1' THEN
                    next_state <= GOT101;
                ELSE next_state <= IDLE;
                END IF;
            WHEN GOT101 =>
                IF data = '1' THEN
                    next_state <= GOT1;
                ELSE 
                    next_state <= GOT10;
                END IF;
            WHEN OTHERS => NULL;
        END CASE;
    END PROCESS NEXTSTATE;
    result <= '1' WHEN (current_state = GOT101 and data = '1') ELSE '0';
END beh;

但是，我的模拟结果不正确。你能帮我解决这个问题吗？非常感谢。

---

您只需将Mealy输出写入流程的transition if-then-else分支

NEXTSTATE: PROCESS(data, current_state)
BEGIN
    -- default assignments
    next_state <= state;       -- so your code won't create latches
    result     <= '0';         -- result is always 0, except of transition GOT101 to GOT1

    CASE current_state IS
        WHEN IDLE =>
            IF data = '1' THEN
                next_state <= GOT1;
            ELSE next_state <= IDLE;
            END IF;
        WHEN GOT1 =>
            IF data = '0' THEN
                next_state <= GOT10;
            ELSE next_state <= GOT1;
            END IF;
        WHEN GOT10 =>
            IF data = '1' THEN
                next_state <= GOT101;
            ELSE next_state <= IDLE;
            END IF;
        WHEN GOT101 =>
            IF data = '1' THEN
                result     <= '1';
                next_state <= GOT1;
            ELSE 
                next_state <= GOT10;
            END IF;
        WHEN OTHERS => NULL;
    END CASE;
END PROCESS NEXTSTATE;

NEXTSTATE:进程（数据、当前状态）
开始
--默认分配
下一个状态你会不断从那些似乎认为结果有问题的人那里得到答案

问题在于
数据
与
时钟
不同步。到处都有转换，mealy输出正在做它应该做的事情

这是一个组合输出，不应该用作时钟。它可用作在
clk
上运行的寄存器的启用或输入

这里有一个测试台，供我们这些没有Modelsim的人使用：

library ieee;
use ieee.std_logic_1164.all;

entity mealy_1011_tb is
end entity;

architecture foo of mealy_1011_tb is
    signal rst_n:     std_logic := '0';
    signal  clk:      std_logic := '1';
    signal  data:     std_logic := '0';
    signal  result:   std_logic;
begin
DUT:
    entity work.mealy_detector_1011
    port map (
        rst_n => rst_n,
        clk => clk,
        data => data,
        result => result
    );
CLOCK:
    process
    begin
        wait for 50 ns;
        clk <= not clk;
        if Now > 799 ns then
            wait;
        end if;
    end process;
STIMULUS:
    process
    begin
        wait for 10 ns;
        rst_n <= '1';
        wait for 70 ns;   
        data <= '1';     --  80 ns
        wait for 100 ns;
        data <= '0';     -- 180 ns
        wait for 50 ns;
        data <= '1';     -- 230 ns
        wait for 100 ns;
        data <= '0';     -- 330 ns
        wait for 140 ns;
        data <= '1';     -- 470 ns
        wait for 60 ns;
        data <= '0';     -- 530 ns
        wait for 40 ns;   
        data <= '1';     -- 570 ns
        wait for 50 ns;
        data <= '0';     -- 620 ns
        wait;
    end process;
end architecture;

ieee库；
使用ieee.std_logic_1164.all；
实体mealy_1011_tb为
终端实体；
mealy_1011_tb的架构是
信号rst_n:std_逻辑：='0'；
信号时钟：标准逻辑：='1'；
信号数据：标准逻辑：='0'；
信号结果：std_逻辑；
开始
DUT：
实体工作.mealy_探测器_1011
港口地图(
rst\u n=>rst\u n，
时钟=>clk，
数据=>数据，
结果=>result
);
时钟：
过程
开始
等待50纳秒；
时钟799纳秒
等待
如果结束；
结束过程；
刺激：
过程
开始
等待10纳秒；
首先，我将提供一个试验台。模拟您的过程。它会得到同样的答案。不需要对下一个状态进行默认分配。为了证明这一点，请将其他案例注释掉。注意
下一个\u状态
被分配到每个位置。（
state
在案例陈述中有完整的覆盖范围，每个if和else都有一个分配到
next_state
）@DavidKoontz抱歉，我错过了其他人的
行。当然，下一个州你能给我你的密码吗？我的英语不好。我不能清楚地理解你的评论。你能帮助我吗？非常感谢你！
library ieee;
use ieee.std_logic_1164.all;

entity mealy_1011_tb is
end entity;

architecture foo of mealy_1011_tb is
    signal rst_n:     std_logic := '0';
    signal  clk:      std_logic := '1';
    signal  data:     std_logic := '0';
    signal  result:   std_logic;
begin
DUT:
    entity work.mealy_detector_1011
    port map (
        rst_n => rst_n,
        clk => clk,
        data => data,
        result => result
    );
CLOCK:
    process
    begin
        wait for 50 ns;
        clk <= not clk;
        if Now > 799 ns then
            wait;
        end if;
    end process;
STIMULUS:
    process
    begin
        wait for 10 ns;
        rst_n <= '1';
        wait for 70 ns;   
        data <= '1';     --  80 ns
        wait for 100 ns;
        data <= '0';     -- 180 ns
        wait for 50 ns;
        data <= '1';     -- 230 ns
        wait for 100 ns;
        data <= '0';     -- 330 ns
        wait for 140 ns;
        data <= '1';     -- 470 ns
        wait for 60 ns;
        data <= '0';     -- 530 ns
        wait for 40 ns;   
        data <= '1';     -- 570 ns
        wait for 50 ns;
        data <= '0';     -- 620 ns
        wait;
    end process;
end architecture;